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MF297-07
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CMOS 4 BIT SINGLE CHIP MICROCOMPUTER
S1C6200/6200A
Core CPU Manual
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NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level re
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The information of the product number change Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative. Configuration of product number Devices S1 C 60N01 F 0A01 00 Packing specification Specification Package (D: die form; F: QFP) Model number Model name (C: microcomputer, digital products) Product classification (S1: semiconductor) Developme
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CONTENTS S1C6200/6200A Core CPU Manual CONTENTS 1DESCRIPTION ____________________________________________________ 1 1.1 System Features ........................................................................................................ 1 1.2 Instruction Set Features ........................................................................................... 1 1.3 Differences between S1C6200 and S1C6200A ......................................................... 1 2MEMORY AND OPERATIONS ______
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1 DESCRIPTION 1DESCRIPTION The S1C6200/6200A is the Core CPU of the S1C62 Family of CMOS 4-bit single-chip microcomput- ers. The CPU features a highly-integrated architecture. Memory-mapped peripheral circuits can include RAM, ROM, I/O ports, interrupt controllers, timers and LCD drivers, depending upon the application. The memory address space is divided into program and data memory, each with data and address lines. Program memory consists of on-chip ROM, containing instructions to be execute
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1 DESCRIPTION 4-bit address bus Data Memory XP (4) RAM, Peripheral I/O (4,096 4-bit words max.) YP (4) Oscillator RP (4) Interrupt Timing Controller Generator YHL (8) XHL (8) A (4) B (4) Stack Pointer (8) Program Counter Block TEMPB (5) TEMPA (5) ALU Micro-Instructions I DZC Instruction Decorder Instruction Register (12) S1C6200 CORE CPU 12-bit data bus Program Memory ROM (8,192 12-bit words max.) Fig. 1.1 Block diagram 2 EPSON S1C6200/6200A CORE CPU MANUAL 13-bit address bus 8-bit address b
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2 MEMORY AND OPERATIONS 2MEMORY AND OPERATIONS A single-chip microcomputer using the S1C6200/6200A Core CPU has four major blocks: the program memory (ROM), the data memory (RAM and I/O), the arithmetic logic unit (ALU) and the timing generator circuit. This section describes each of these blocks in detail. 2.1 Program Memory (ROM) Program memory contains the instructions that the CPU executes. Figure 2.1.1 shows the configuration of the program memory. Each instruction is a 12-bit word. Progra
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2 MEMORY AND OPERATIONS 2.1.1 Program counter block The program counter is used to point to the next instruction step to be executed by the CPU. See Figure 2.1.1.1. The program counter has the following registers. Table 2.1.1.1 Program counter registers Register Size PCB (Program Counter-Bank) 1-bit register PCP (Program Counter-Page) 4-bit counter PCS (Program Counter-Step) 8-bit counter NBP (New Bank Pointer) 1-bit register NPP (New Page Pointer) 4-bit register Program memory (8,192 12-bit
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2 MEMORY AND OPERATIONS 2.1.3 Jump instructions A jump can be made using the instructions in Table 2.1.3.1. Table 2.1.3.1 Jump instructions Type of jump Instruction Unconditional JP Conditional JP C, JP NC, JP Z, JP NZ Subroutine call CALL, CALZ Return RET, RETS, RETD Page set PSET Indirect JPBA The differences between jumps within the same page and jumps from one page to another is as follows. • Jumps within the same page A jump can be made within the same page using any of the followin
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2 MEMORY AND OPERATIONS 2.1.6 PSET instruction Jump or call instructions must follow PSET immediately in order for PSET to affect the destination address. When a jump or call is not immediately preceded by PSET, the destination address is within the current page. Some examples using PSET are shown in Table 2.1.6.1. Table 2.1.6.1 PSET examples Bank Page Stap Instruction Operation 0 01H 10H PSET 13H 0 01H 11H JP 08H The program jumps to bank 1, page 3, step 8. • • • • • • • • 0 01H 21H PSET 15H
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2 MEMORY AND OPERATIONS The difference between CALL and CALZ is shown in Figure 2.1.7.2. CALL with PSET Bank 0 Page 15 Bank 1 Page 15 Bank 0 Bank 1 can go anywhere Bank 0 Page 14 Bank 1 Page 14 within a bank Step 0 Step 0 Step 1 Step 1 CALL PSET Bank 0 Page 3 Bank 1 Page 3 CALL CALZ Bank 0 Page 1 Bank 1 Page 1 Step 254 Step 254 Bank 0 Page 0 Bank 1 Page 0 Step 255 Step 255 Step 0 Step 0 CALZ Step 1 Step 1 CALL without PSET can go anywhere CALL and CALZ in a page cannot go Step 254 Step 254 betw
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2 MEMORY AND OPERATIONS 2.2 Data Memory The data memory area comprises 4,096 4-bit words. The RAM, timer, I/O and other peripheral circuits are mapped into this memory according to the designer's specifications. Figure 2.2.1 shows the data memory configuration. Page 15 Page 14 Step 0 Step 1 RP XHL or YHL Page 0 (within page) Page 3 only
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2 MEMORY AND OPERATIONS • Index register IY MSB LSB Index register IY is like the index register IX: it has a 4 44 4-bit page part (YP), an 8-bit register (YHL), and can address any location in the data memory. See Figure YP YH YL 2.2.1.2. YHL YHL is divided into two 4-bit groups: the four high- IY order bits (YH) and the four low-order bits (YL), and can address any location within a page. Fig. 2.2.1.2 The configuration of the index register IY – MY is the data memory location whose address
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2 MEMORY AND OPERATIONS 2.3 ALU (Arithmetic Logic Unit) and Registers Table 2.3.1 shows ALU operations between the 4-bit registers, TEMPA and TEMPB. Table 2.3.1 ALU register operation Operation Instruction Add, without carry ADD Add, with carry ADC Subtract, without borrow SUB Subtract, with borrow SBC Logical-AND AND Logical-OR OR Exclusive-OR XOR Comparison CP Flag bit test FAN Rotate right, with carry RRC Rotate left, with carry RLC Invert NOT The Z (zero) flag is set when the result of ALU
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2 MEMORY AND OPERATIONS Hexadecimal operations will not always produce the correct result if performed in decimal mode. Note that: • An add instruction with carry (for example, ADC XH,i) which uses index registers XH, XL, YH and YL, does not involve decimal correction even if it is performed in the decimal mode. This is because it uses an 8-bit field for 4-bit data. • The results of the compare instruction (CP) is not decimal-corrected, because the carry flag is ignored. • The result of t
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2 MEMORY AND OPERATIONS 2.5 Interrupts The S1C6200/6200A can have up to 15 interrupt vectors. When used with peripheral circuits, these allow internal and external interrupts to be processed easily. See Figure 2.5.3.1 through 2.5.3.4. 2.5.1 Interrupt vectors The interrupt vectors are assigned to steps 1 to 15 in page 1 of each bank of the program memory. When an interrupt occurs, the program jumps to the appropriate interrupt vector in the current bank. The priority and linking of these vectors
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2 MEMORY AND OPERATIONS S1C6200 Clock Status 5-clock Instrruction 12-clock Instrruction INT1 (*1) INT2 (*1) JP (*2) Instruction Interrupt Interrupt processing: 12-clock instruction ... 13 to 25 clock cycles 7-clock instruction ... 13 to 20 clock cycles 5-clock instruction ... 13 to 18 clock cycles S1C6200A Clock Status Instruction 5-clock Instrruction 12-clock Instrruction INT1 (*1) INT2 (*1) JP (*2) Interrupt Interrupt processing: 12-clock instruction ... 12.5 to 24.5 clock cycles 7-clock inst
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2 MEMORY AND OPERATIONS S1C6200/6200A System clock CPU clock Status Instruction 5-clock Instrruction SLEEP INT1 (*1) INT2 (*1) JP (*2) Interrupt Interrupt processing: 14 to 15 clock cycles Status: Fetch Execute Note: (*1) INT1 and INT2 are dummy instructions (*2) Branches to the top of the interrupt service routine Fig. 2.5.3.3 Interrupt timing in SLEEP mode S1C6200 Clock Status PSET CALL INT1 (*1) INT2 (*1) JP (*2) Instruction Interrupt Interrupt processing: PSET + CALL ... 13 to 25 clock cyc
