Inhaltszusammenfassung zur Seite Nr. 1
FUJITSU SEMICONDUCTOR
DATA SHEET
32-Bit Proprietary Microcontroller
LSI Network Security System
MB91401
nnnn DESCRIPTION
The MB91401 is a network security LSI incorporating a Fujitsu’s 32-bit, FR-family RISC microcontroller with 10/
100Base-T MAC Controller, encryption function and authentication function. The LSI contains an encryption
authentication hardware accelerator that boosts the LSI’s performance for encryption and authentication commu-
nication (IKE/IPsec/SSL) to be demanded further.
Inhaltszusammenfassung zur Seite Nr. 2
MB91401 • For DES-ECB/DES-CBC/3DES-ECB/3DES-CBC mode* • For MD5/SHA-1/HMAC-MD5/HMAC-SHA-1 mode • DH group: for 1 (MODP 768 bit) /2 (1024 bit) For the encryption/authentication macros, a software library is available by contacting the Fujitsu sales repre- sentative as required. * : Encryption function (DES/3DES) Method to encrypt, and to decrypt plaintext in 64 bits with code and decoding key to 56 bits. (3DES is repeated three times. The key can be set by 168 bits or less.) • Packet filterin
Inhaltszusammenfassung zur Seite Nr. 3
MB91401 (Continued) • • • • CARD Interface (CompactFlash) The CompactFlash interface is a memory and I/O mode correspondence. It corresponds to the I/O of data such as not only the memory card but also the communication cards. 2 • • • • I C Interface • Master/slave sending and receiving • For standard mode (100 Kbps Max) 3
Inhaltszusammenfassung zur Seite Nr. 4
MB91401 nnnn PIN ASSIGNMENT INDEX 1 2 3 4 5 6 7 8 9 1011 1213 1415 1617 1819 A 1 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 B 2 73 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 54 C 3 74 137 192 191 190 189 188 187 186 185 184 183 182 181 180 179 120 53 D 4 75 138 193 240 239 238 237 236 235 234 233 232 231 230 229 178 119 52 E 5 76 139 194 228 177 118 51 F 6 77 140 195 227 176 117 50 G 7 78 141 196 226 175 116 49 H 8 79 142 197 225 174 115 48 J 9 80 143 198 (TOP-VIE
Inhaltszusammenfassung zur Seite Nr. 5
MB91401 nnnn PIN NUMBER TABLE Pin Number Pin name Pin Number Pin name Pin Number Pin name Pin Number Pin name 1 VSS 61 UDP 121 EXD11 181 SDA 2 CFD15 62 CFWEX 122 EXD14 182 USBINS 3 ICLK 63 CFCE1X 123 CFCD2X 183 UDM 4 ICS0 64 CFIORDX 124 UCLKSEL 184 CFRESET 5 TDI 65 CFA1 125 CFWAITX 185 CFREGX 6 UCLK48 66 CFA5 126 N.C. 186 CFA0 7 TMS 67 CFA8 127 CFOEX 187 CFA3 8 XINI 68 CFD0 128 CFCE2X 188 CFA7 9 PLLBYPAS 69 CFD3 129 CFIOWRX 189 CFA10 10 OSCEB 70 CFD7 130 CFA2 190 CFD2 11 TEST0 71 CFD10 131 CFA6
Inhaltszusammenfassung zur Seite Nr. 6
MB91401 nnnn PIN DESCRIPTION [SYSTEM] [ETHERNET MAC CONTROLLER] XINI 1 TXCLK 1 INITXI 1 TXD3 to TXD0 4 NMIX 1 TXEN 1 INT7 to INT5 3 RXCLK 1 MDI2 to MDI0 3 RXER 1 [OSCILLATOR] RXD3 to RXD0 4 OSCEA 1 RXDV 1 OSCC 1 RXCRS 1 OSCEB 1 COL 1 MB91401 [PLL CONTROL] MDCLK 1 PLLS 1 MDIO 1 PLLSET1, PLLSET0 2 [EXTERNAL IF] PLLBYPAS 1 EXCSX 1 CLKSEL 1 EXA 1 [ICE] EXD15 to EXD0/GPIO7 to GPIO0 16 Signal line 196 pin BREAKI 1 EXRDX 1 ICS2 to ICS0 3 EXWRX 1 ICLK 1 DREQRX 1 Power Supply/ 39 pin ICD3 to ICD0 4 DREQT
Inhaltszusammenfassung zur Seite Nr. 7
MB91401 SYSTEM (9 pin) Pin name Pin no. Polarity I/O Circuit Function/application Clock input pin XINI 8 IN D Input pin of clock generated in clock generator. 10 MHz to 50 MHz frequency can be input. Reset input pin This pin inputs a signal to initialize the LSI. Nega- When turning on the power supply, apply “0” to the pin until INITXI 204 IN D the clock signal input to the CLKIN pin becomes stable. tive All built-in registers and external pins are initialized, and the built-in PLL is sto
Inhaltszusammenfassung zur Seite Nr. 8
MB91401 ICE (9 pin) Pin name Pin no. Polarity I/O Circuit Function/application Emulator break request pin BREAKI 76 IN D This pin inputs the emulator break request when an ICE is connected. ICS2 74 Emulator chip status pins ICS1 75 OUT F These pins output the emulator status when an ICE is ICS0 4 connected. Emulator clock pin ICLK 3 I/O B This pin serves as the emulator clock pin when an ICE is connected. ICD3 140 Emulator data pins ICD2 194 I/O B These pins serve as the emulator dat
Inhaltszusammenfassung zur Seite Nr. 9
MB91401 UART (6 pin) Pin name Pin no. Polarity I/O Circuit Function/application SIN1 85 Serial data input pins IN D SIN0 15 Serial data input pin of UART built-in FR core. SOUT1 149 Serial data output pins OUT F SOUT0 86 Serial data output pin of UART built-in FR core. SCK1 148 Serial clock I/O pins I/O B SCK0 14 Serial clock input/output pin of UART built-in FR core. MEMORY IF (66 pin) Pin name Pin no. Polarity I/O Circuit Function/application A23 156 A22 95 A21 26 A20 155 A19 94 A18
Inhaltszusammenfassung zur Seite Nr. 10
MB91401 (Continued) Pin name Pin no. Polarity I/O Circuit Function/application D31 169 D30 110 D29 168 D28 109 D27 42 D26 218 D25 167 D24 108 D23 41 D22 166 D21 107 D20 40 D19 106 D18 39 D17 38 D16 105 Data input/output pins I/O B D15 36 32 bits data input/output signal pin. D14 165 D13 104 D12 35 D11 164 D10 103 D9 34 D8 216 D7 163 D6 102 D5 33 D4 162 D3 101 D2 32 D1 100 D0 31 CSX6 159 Chip select output pins Nega- CSX1 98 OUT B 3-bit chip select signal pin. tive CSX0 29 Output the “L” level
Inhaltszusammenfassung zur Seite Nr. 11
MB91401 ETHERNET MAC CONTROLLER (17 pin) Pin name Pin no. Polarity I/O Circuit Function/application Clock input for reception pin RXCLK 48 IN D MII sync signal during reception. The frequency is 2.5 MHz at 10 Mbps and 25 MHz at 100 Mbps. Receive error input pin Posi- RXER 113 IN D It is recognized that there is an error in the reception packet tive when “1” is input from the PHY device at receiving. Posi- Receive data valid input pin RXDV 172 IN D tive It is recognized that receive data i
Inhaltszusammenfassung zur Seite Nr. 12
MB91401 EXTERNAL IF (23 pin) Pin name Pin no. Polarity I/O Circuit Function/application Nega- External chip select input pin EXCSX 50 IN D tive Chip select input pin from external host. External address input pin Address input pin from external host. EXA 116 IN D “0” : Register select “1” : FIFO data select EXD15 180 EXD14 122 EXD13 57 External data input/output pins EXD12 56 I/O B The I/O terminal of data bus bit of bit15 to bit8 with an EXD11 121 external host. EXD10 54 EXD9 179 EXD8
Inhaltszusammenfassung zur Seite Nr. 13
MB91401 USB IF (5 pin) Pin name Pin no. Polarity I/O Circuit Function/application USB data D + (differential) pin I/O signal pin on the plus side of the USB data. Use the LSI with 25 W to 30 W (27 W recommended) UDP 61 I/O C external series load resistors, 1.5 kW pull-up resistors and about 100 kW resistors. Input “0” when the USB macro is unused. USB data D - (differential) pin I/O signal pin on the minus side of the USB data. Use the LSI with 25 W to 30 W (27 W recommended) UDM 183
Inhaltszusammenfassung zur Seite Nr. 14
MB91401 CARD IF (41 pin) Pin name Pin no. Polarity I/O Circuit Function/application CFD15 2 CFD14 73 CFD13 72 CFD12 137 CFD11 136 CFD10 71 CFD9 192 CF data input/output pins CFD8 135 I/O B I/O data/status/command signal pin to CompactFlash card CFD7 70 side CFD6 240 CFD5 191 CFD4 134 CFD3 69 CFD2 190 CFD0 133 CFD0 68 CFA10 189 CFA9 132 CFA8 67 CFA7 188 CFA6 131 CF address 10 to 0 output pins CFA5 66 OUT B Address output CFA10 to CFA0 pins to CompactFlash card CFA4 236 side CFA3 187 CFA2 1
Inhaltszusammenfassung zur Seite Nr. 15
MB91401 (Continued) Pin name Pin no. Polarity I/O Circuit Function/application Card connection detect input pin : CFCD1X Nega- Checking connection pin of the socket and CompactFlash CFCD1X 58 IN E tive card. It is shown that the CompactFlash card was connected when this signal and CFCD2X are both input by “0”. CF side GND input pin GND level detection pin from CompactFlash side. Nega- CFVS1X 230 IN E The “0” input to the pin assumes that the CompactFlash tive card can operate at 3.3 V, sett
Inhaltszusammenfassung zur Seite Nr. 16
MB91401 2 I C IF (2 pin) Pin name Pin no. Polarity I/O Circuit Function/application Serial data line input/output pin SDA 181 I/O B 2 I C bus data I/O pin Serial clock line input/output pin SCL 59 I/O B 2 I C bus clock I/O pin Power Supply/GND (39 pin) Pin name Pin no. Polarity I/O Circuit Function/application Power APLL dedicated power supply pin PLLVDD 199 V-E supply This pin is for 1.8 V power supply pin. PLLVSS 197 GND V-S APLL dedicated GND Pin 83 196 202 208 Power VDDE 214 V-E
Inhaltszusammenfassung zur Seite Nr. 17
MB91401 nnnn I/O CIRCUIT TYPE Type Circuit Remarks Digital output • With pull/down • CMOS level output A • CMOS level input Digital output • Value of pull-down resistance = approx. 33 kW (Typ) Digital input Digital output] • CMOS level output B • CMOS level input Digital output Digital input + D input - D input D+ Differential input D- + Full D output C USB I/O - Full D output + Low D output - Low D output Direction Speed (Continued) 17
Inhaltszusammenfassung zur Seite Nr. 18
MB91401 (Continued) Type Circuit Remarks D CMOS level input Digital input • With pull-up • CMOS level input E • Value of pull-up resistance = approx. 33 kW (Typ) Digital input Digital output F CMOS level output Digital output Oscillation output Control G Oscillation circuit 18
Inhaltszusammenfassung zur Seite Nr. 19
MB91401 nnnn HANDLING DEVICES Preventing Latch-up When a voltage that is higher than VDDE and a voltage that is lower than VSS are impressed to the input terminal and the output terminal in CMOS IC or the voltage that exceeds ratings between VDDE to VSS is impressed, the latch-up phenomenon might be caused. If latch-up occurs, the supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Use meticulous care not to let any voltage exceed the maximum rating during d
Inhaltszusammenfassung zur Seite Nr. 20
MB91401 Figure When you share the power supply for digital and for VCO VDD (for digital) LSI PLLVDD (for VCO) APLL Logic part Power PLLVSS supply (a) VSS Treatment of the unused pins Leaving unused input pins open results in a malfunction, so process the pull-up or pull-down. Treatment of OPEN pins Be sure to use open pins in open state. Treatment of output pins A large current may flow to an output pin left connected to the power-supply, another output pin, or to a high capacitance load. L
