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CY7C1353G
4-Mbit (256K x 18) Flow-through SRAM
with NoBL™ Architecture
[1]
Features Functional Description
• Supports up to 133-MHz bus operations with zero wait The CY7C1353G is a 3.3V, 256K x 18 Synchronous
states Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
— Data is transferred on every clock
insertion of wait states. The CY7C1353G is equipped with the
• Pin compatible and functionally equivalent to ZBT™ devices
advan
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CY7C1353G Selection Guide 133 MHz 100 MHz Unit Maximum Access Time 6.5 8.0 ns Maximum Operating Current 225 205 mA Maximum CMOS Standby Current 40 40 mA Pin Configuration 100-Pin TQFP Pinout NC 1 80 A NC 2 79 NC NC 3 78 NC V 4 77 DDQ V DDQ V 5 76 SS V SS NC 6 75 NC 7 NC 74 DQP A 8 DQ 73 DQ B A 9 DQ 72 B DQ A 10 V 71 V SS SS 11 V 70 DDQ V DDQ 12 DQ 69 DQ B A 13 DQ 68 B DQ A CY7C1353G 14 NC 67 V SS 15 V 66 DD NC BYTE B 16 NC 65 V DD 17 V 64 ZZ BYTE A SS 18 DQ 63 DQ B A 19 DQ 62 B DQ A 20 V 61 V
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CY7C1353G Pin Definitions Name IO Description A , A , A Input- Address Inputs used to select one of the 256K address locations. Sampled at the rising edge 0 1 Synchronous of the CLK. A are fed to the two-bit burst counter. [1:0] BW Input- Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on [A:B] Synchronous the rising edge of CLK. WE Input- Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This Synchronous signal
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CY7C1353G Therefore, the type of access (Read or Write) is maintained Functional Overview throughout the burst sequence. The CY7C1353G is a synchronous flow-through burst SRAM Single Write Accesses designed specifically to eliminate wait states during Write-Read transitions. All synchronous inputs pass through Write access are initiated when these conditions are satisfied input registers controlled by the rising edge of the clock. The at clock rise: clock signal is qualified with the Clock Enabl
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CY7C1353G Interleaved Burst Address Table Linear Burst Address Table (MODE = GND) (MODE = Floating or V ) DD First Second Third Fourth Address Address Address Address First Second Third Fourth A1, A0 A1, A0 A1, A0 A1, A0 Address Address Address Address A1, A0 A1, A0 A1, A0 A1, A0 00 01 10 11 00 01 10 11 01 10 11 00 01 00 11 10 10 11 00 01 10 11 00 01 11 00 01 10 11 10 01 00 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit I Sleep mode standby current ZZ >
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CY7C1353G [2, 3, 9] Partial Truth Table for Read/Write Function WE BW BW A B Read HX X Write – No bytes written L H H Write Byte A – (DQ and DQP)LLH A A Write Byte B – (DQ and DQP)LHL B B Write All Bytes L L L Note: 9. Table only lists a partial listing of the byte write combinations. Any combination of BW[A:D] is valid. Appropriate write is based on which byte write is active. Document #: 38-05515 Rev. *E Page 6 of 13 [+] Feedback
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CY7C1353G Maximum Ratings DC Input Voltage ................................... –0.5V to V + 0.5V DD Exceeding maximum ratings may impair the useful life of the Current into Outputs (LOW)......................................... 20 mA device. These user guidelines are not tested. Static Discharge Voltage.......................................... > 2001V Storage Temperature .................................–65°C to +150°C (MIL-STD-883, Method 3015) Ambient Temperature with Latch up Current........
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CY7C1353G [12] Capacitance 100 TQFP Parameter Description Test Conditions Max Unit C Input Capacitance T = 25°C, f = 1 MHz, 5pF IN A V = 3.3V DD C Clock Input Capacitance 5 pF CLOCK V =3.3V DDQ C IO Capacitance 5 pF IO [12] Thermal Resistance 100 TQFP Parameters Description Test Conditions Package Unit Θ Thermal Resistance Test conditions follow standard test methods and 30.32 °C/W JA (Junction to Ambient) procedures for measuring thermal impedance, according to EIA/JESD51. Θ Thermal Resistanc
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CY7C1353G [17, 18] Switching Characteristics Over the Operating Range –133 –100 Parameter Description Min Max Min Max Unit [13] t V (Typical) to the first Access 11 ms POWER DD Clock t Clock Cycle Time 7.5 10 ns CYC t Clock HIGH 2.5 4.0 ns CH t Clock LOW 2.5 4.0 ns CL Output Times t Data Output Valid After CLK Rise 6.5 8.0 ns CDV t Data Output Hold After CLK Rise 2.0 2.0 ns DOH [14, 15, 16] t Clock to Low-Z 00 ns CLZ [14, 15, 16] t Clock to High-Z 3.5 3.5 ns CHZ t OE LOW to Output Valid 3.5 3.5
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CY7C1353G Switching Waveforms [19, 20, 21] Read/Write Waveforms t 123 456789 10 CYC CLK t t t t CENS CENH CL CH CEN t t CES CEH CE ADV/LD WE BW[A:B] A1 A2 A3 A4 A5 A6 A7 ADDRESS t CDV t t AS AH t t t t DOH OEV CLZ CHZ D(A1) D(A2) D(A2+1) Q(A3) Q(A4) Q(A4+1) D(A5) Q(A6) D(A7) DQ t OEHZ t t DS DH t DOH t OELZ OE COMMAND WRITE WRITE BURST READ READ BURST WRITE READ WRITE DESELECT D(A1) D(A2) WRITE Q(A3) Q(A4) READ D(A5) Q(A6) D(A7) D(A2+1) Q(A4+1) DON’T CARE UNDEFINED Notes: For this waveform ZZ i
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CY7C1353G Switching Waveforms [19, 20, 22] NOP, STALL and DESELECT Cycles 123 456 789 10 CLK CEN CE ADV/LD WE BW[A:B] A1 A2 A3 A4 A5 ADDRESS t CHZ D(A1) Q(A2) Q(A3) D(A4) Q(A5) DQ t DOH COMMAND WRITE READ STALL READ WRITE STALL NOP READ DESELECT CONTINUE D(A1) Q(A2) Q(A3) D(A4) Q(A5) DESELECT DON’T CARE UNDEFINED [23,24] ZZ Mode Timing CLK t t ZZ ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI ALL INPUTS DESELECT or READ Only (except ZZ) Outputs (Q) High-Z DON’T CARE Notes: 22.The IGNORE CLOCK EDGE or ST
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CY7C1353G Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed Package Operating (MHz) Ordering Code Diagram Part and Package Type Range 133 CY7C1353G-133AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial CY7C1353G-133AXI lndustrial 100 CY7C1353G-100AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial
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CY7C1353G Document History Page Document Title: CY7C1353G 4-Mbit (256K x 18) Flow-through SRAM with NoBL™ Architecture Document Number: 38-05515 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 224363 See ECN RKF New data sheet *A 288431 See ECN VBL Deleted 66 MHz Changed TQFP package in Ordering Information section to Pb-free TQFP *B 333626 See ECN SYT Removed 117-MHz speed bin Modified Address Expansion balls in the pinouts for 100 TQFP Packages according to JEDEC standards a
