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TMS320DM646x DMSoC
Asynchronous External Memory Interface
(EMIF)
User's Guide
Literature Number: SPRUEQ7C
February 2010
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2 SPRUEQ7C–February 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
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Preface ....................................................................................................................................... 6 1 Introduction ........................................................................................................................ 8 1.1 Purpose of the Peripheral .............................................................................................. 8 1.2 Features ............................................................................
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www.ti.com List of Figures 1 EMIF Functional Block Diagram .......................................................................................... 9 2 EMIF Asynchronous Interface ........................................................................................... 11 3 EMIF to 8-bit and 16-bit Memory Interfaces ........................................................................... 11 4 Timing Waveform of an Asynchronous Read Cycle in Normal Mode ....................................
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www.ti.com List of Tables 1 EMIF Pins .................................................................................................................. 10 2 Behavior of EM_CS Signal Between Normal Mode and Select Strobe Mode..................................... 10 3 Description of the Asynchronous Configuration Register (ACFGn)................................................. 12 4 Description of the Asynchronous Wait Cycle Configuration Register (AWCCR).................................. 13 5 De
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Preface SPRUEQ7C–February 2010 Read This First About This Manual This document describes the asynchronous external memory interface (EMIF) in the TMS320DM646x Digital Media System-on-Chip (DMSoC). The EMIF supports a glueless interface to a variety of external devices. Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. • Registers in this document are shown
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www.ti.com Related Documentation From Texas Instruments SPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache. 7 SPRUEQ7C–February 2010 Read This First Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
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User's Guide SPRUEQ7C–February 2010 Asynchronous External Memory Interface (EMIF) 1 Introduction This document describes the operation of the asynchronous external memory interface (EMIF) in the TMS320DM646x Digital Media System-on-Chip (DMSoC). 1.1 Purpose of the Peripheral The purpose of this EMIF is to provide a means to connect to a variety of external devices including: • NAND Flash • Asynchronous devices including Flash and SRAM • Host processor interfaces such as the host port interface (
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www.ti.com Architecture 1.3 Functional Block Diagram Figure 1 illustrates the connections between the EMIF and its internal requesters, along with the external EMIF pins. Section 2.2 contains a description of the entities internal to the device that can send requests to the EMIF, along with their prioritization. Section 2.3 describes the EMIF's external pins and summarizes their purpose when interfacing with SDRAM and asynchronous devices. Figure 1. EMIF Functional Block Diagram EMIF VICP EM_CS[
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Architecture www.ti.com 2.3 Signal Descriptions Table 1 describes the function of each of the EMIF pins. Table 1. EMIF Pins Pins(s) I/O Description EM_ A[22:0] O EMIF address bus. These pins are used in conjunction with the EM_BA pins to form the address that is sent to the device. EM_BA[1:0] O EMIF bank address. These pins are used in conjunction with the EM_A pins to form the address that is sent to the device. EM_CS[5:2] O Active-low chip enable pin for asynchronous devices. These pins are me
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www.ti.com Architecture 2.5.1 Interfacing to Asynchronous Memory Figure 2 shows the EMIF's external pins used in interfacing with an asynchronous device. Of special note is the connection between the EMIF and the external device's address bus. The EMIF address pin EM_A[0] always provides the least significant bit of a 32-bit word address. Therefore, when interfacing to a 16-bit or 8-bit asynchronous device, the EM_BA[1] and EM_BA[0] pins provide the least-significant bits of the halfword or byte
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Architecture www.ti.com 2.5.2 Programmable Asynchronous Parameters The EMIF allows a high degree of programmability for shaping asynchronous accesses. The programmable parameters are: • Setup: The time between the beginning of a memory cycle (address valid) and the activation of the output enable or write enable strobe • Strobe: The time between the activation and deactivation of output enable or write enable strobe. • Hold: The time between the deactivation of output enable or write enable stro
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www.ti.com Architecture Table 3. Description of the Asynchronous Configuration Register (ACFGn) (continued) Parameter Description ASIZE Asynchronous Device Bus Width. This field determines the data bus width of the asynchronous interface in the following way: • ASIZE = 0 selects an 8-bit bus • ASIZE = 1 selects a 16-bit bus The configuration of ASIZE determines the function of the EM_A and EM_BA pins as described in Section 2.5.1. This field also determines the number of external accesses requir
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Architecture www.ti.com 2.5.4 Read and Write Operations in Normal Mode Normal mode is the asynchronous interface's default mode of operation. The Normal mode is selected when the SS bit in the asynchronous configuration register (ACFGn) is cleared to 0. In this mode, the EM_CS signal operates as a chip enable signal, active throughout the duration of the memory access. 2.5.4.1 Asynchronous Read Operations (Normal Mode) An asynchronous read is performed when any of the requesters mentioned in Sec
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www.ti.com Architecture Figure 4. Timing Waveform of an Asynchronous Read Cycle in Normal Mode Strobe Setup Hold 3 2 2 Internal clock EM_CS[5:2] EM_A/EM_BA Address EM_D Data EM_OE EM_WE EM_RW 15 SPRUEQ7C–February 2010 Asynchronous External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
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Architecture www.ti.com 2.5.4.2 Asynchronous Write Operations (Normal Mode) An asynchronous write is performed when any of the requesters mentioned in Section 2.2 request a write to asynchronous memory. In the event that the write request cannot be serviced by a single access cycle to the external device, multiple access cycles will be performed by the EMIF until the entire request is fulfilled. The details of an asynchronous write operation in Normal mode are described in Table 8 and an example
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www.ti.com Architecture Figure 5. Timing Waveform of an Asynchronous Write Cycle in Normal Mode Strobe Setup Hold 3 2 2 Internal clock EM_CS[5:2] EM_A/EM_BA Address EM_D Data EM_OE EM_WE EM_RW 17 SPRUEQ7C–February 2010 Asynchronous External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
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Architecture www.ti.com 2.5.5 Read and Write Operations in Select Strobe Mode Select Strobe mode is the EMIF's second mode of operation. The SS mode is selected when the SS bit in the asynchronous configuration register (ACFGn) is set to 1. In this mode, the EM_CS pin functions as a strobe signal and is therefore only active during the strobe period of an access cycle. 2.5.5.1 Asynchronous Read Operations (Select Strobe Mode) An asynchronous read is performed when any of the requesters mentioned
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www.ti.com Architecture Figure 6. Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode Strobe Setup Hold 3 2 2 Internal clock EM_CS[5:2] EM_A/EM_BA Address EM_D Data EM_OE EM_WE EM_RW 19 SPRUEQ7C–February 2010 Asynchronous External Memory Interface (EMIF) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
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Architecture www.ti.com 2.5.5.2 Asynchronous Write Operations (Select Strobe Mode) An asynchronous write is performed when any of the requesters mentioned in Section 2.2 request a write to memory in the asynchronous bank of the EMIF. In the event that the write request cannot be serviced by a single access cycle to the external device, multiple access cycles will be performed by the EMIF until the entire request is fulfilled. The details of an asynchronous write operation in Select Strobe mode a
