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TMS320C6454
Fixed-Point Digital Signal Processor
www.ti.com
SPRS311A–APRIL 2006–REVISED DECEMBER 2006
1 TMS320C6454 Fixed-Point Digital Signal Processor
1.1 Features
• 32-Bit DDR2 Memory Controller (DDR2-533
• High-Performance Fixed-Point DSP (C6454)
SDRAM)
– 1.39-, 1.17-, and 1-ns Instruction Cycle Time
– 720-MHz, 850-MHz, and 1-GHz Clock Rate • EDMA3 Controller (64 Independent Channels)
– Eight 32-Bit Instructions/Cycle
• 32-/16-Bit Host-Port Interface (HPI)
– 8000 MIPS/MMACS (16-Bits)
• 32-Bi
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PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor www.ti.com SPRS311A–APRIL 2006–REVISED DECEMBER 2006 1.1.1 ZTZ/GTZ BGA Package (Bottom View) The TMS320C6454 devices are designed for a package temperature range of 0°C to +90°C (commercial temperature range). ZTZ/GTZ 697-PIN BALL GRID ARRAY (BGA) PACKAGE (BOTTOM VIEW) AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 NOTE: The ZTZ mechan
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TMS320C6454 Fixed-Point Digital Signal Processor www.ti.com SPRS311A–APRIL 2006–REVISED DECEMBER 2006 The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doubles the multiply throughput versus the C64x core by performing four 16-bit x 16-bit multiply-accumulates (MACs) every clock cycle. Thus, eight 16-bit x 16-bit MACs can be executed every c
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PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor www.ti.com SPRS311A–APRIL 2006–REVISED DECEMBER 2006 1.3 Functional Block Diagram Figure 1-2 shows the functional block diagram of the C6454 device. C6454 DDR2 32 DDR2 SDRAM Mem Ctlr PLL2 and PLL2 (D) Controller L2 ROM SBSRAM L1P Cache Direct-Mapped 32K 32K Bytes (E) Bytes ZBT SRAM 64 EMIFA SRAM L1P Memory Controller (Memory Protect/Bandwidth Mgmt) ROM/FLASH I/O Devices C64x+ DSP Core Control Registers Instruction Fetch 16-/32-bit
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TMS320C6454 Fixed-Point Digital Signal Processor www.ti.com SPRS311A–APRIL 2006–REVISED DECEMBER 2006 Contents 1 TMS320C6454 Fixed-Point Digital Signal 5.5 Megamodule Resets ................................ 81 Processor.................................................. 1 5.6 Megamodule Revision............................... 82 1.1 Features .............................................. 1 5.7 C64x+ Megamodule Register Description(s)........ 83 1.1.1 ZTZ/GTZ BGA Package (Bottom View).............
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PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor www.ti.com SPRS311A–APRIL 2006–REVISED DECEMBER 2006 2 Device Overview 2.1 Device Characteristics Table 2-1, provides an overview of the C6454 DSP. The tables show significant features of the C6454 device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. Table 2-1. Characteristics of the C6454 Processor HARDWARE FEATURES C6454 EMIFA (64-bit bus width) 1 (clock source =
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TMS320C6454 Fixed-Point Digital Signal Processor www.ti.com SPRS311A–APRIL 2006–REVISED DECEMBER 2006 Table 2-1. Characteristics of the C6454 Processor (continued) HARDWARE FEATURES C6454 TMX320C6454ZTZ7, (For more details on the C64x+™ DSP part Device Part Numbers TMX320C6454ZTZ8, numbering, see Figure 2-12) TMX320C6454ZTZ 2.2 CPU (DSP Core) Description The C64x+ Central Processing Unit (CPU) consists of eight functional units, two register files, and two data paths as shown in Figure 2-1. The
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PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor www.ti.com SPRS311A–APRIL 2006–REVISED DECEMBER 2006 Other new features include: • SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible. • Compact Instructions - The native instruction si
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TMS320C6454 Fixed-Point Digital Signal Processor www.ti.com SPRS311A–APRIL 2006–REVISED DECEMBER 2006 Even src1 Odd register register file A file A (A0, A2, (A1, A3, src2 .L1 A4...A30) A5...A31) odd dst (D) even dst long src 8 32 MSB ST1b 32 LSB ST1a 8 long src even dst (D) odd dst Data path A .S1 src1 src2 32 (A) dst2 32 (B) dst1 .M1 src1 src2 (C) 32 MSB LD1b 32 LSB LD1a dst .D1 src1 DA1 src2 2x 1x Even
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PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor www.ti.com SPRS311A–APRIL 2006–REVISED DECEMBER 2006 2.3 Memory Map Summary Table 2-2 shows the memory map address ranges of the C6454 device. The external memory configuration register address ranges in the C6454 device begin at the hex address location 0x7000 0000 for EMIFA and hex address location 0x7800 0000 for DDR2 Memory Controller. Table 2-2. C6454 Memory Map Summary MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS R
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TMS320C6454 Fixed-Point Digital Signal Processor www.ti.com SPRS311A–APRIL 2006–REVISED DECEMBER 2006 Table 2-2. C6454 Memory Map Summary (continued) MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE Reserved 256M 2000 0000 - 2FFF FFFF McBSP 0 Data 256 3000 0000 - 3000 00FF Reserved 64M - 256 3000 0100 - 33FF FFFF McBSP 1 Data 256 3400 0000 - 3400 00FF Reserved 64M - 256 3400 0100 - 37FF FFFF Reserved 2K 3C00 0000 - 3C00 07FF Reserved 16M - 2K 3C00 0800 - 3CFF FFFF Reserved 48M 3D00
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PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor www.ti.com SPRS311A–APRIL 2006–REVISED DECEMBER 2006 2.4 Boot Sequence The boot sequence is a process by which the DSP's internal memory is loaded with program and data sections and the DSP's internal registers are programmed with predetermined values. The boot sequence is started automatically after each power-on reset, warm reset, and system reset. For more details on the initiators of these resets, see Section 7.6, Reset Control
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TMS320C6454 Fixed-Point Digital Signal Processor www.ti.com SPRS311A–APRIL 2006–REVISED DECEMBER 2006 such as Code Composer Studio. For the PCI host boot, the CPU is out of reset, but it executes an IDLE instruction until a DSP interrupt is generated by the host. The host can generate a DSP interrupt through the PCI peripheral by setting the DSPINT bit in the Back-End Application Interrupt Enable Set Register (PCIBINTSET) and the Status Set Register (PCISTATSET). Note that the HPI host boot is a
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PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor www.ti.com SPRS311A–APRIL 2006–REVISED DECEMBER 2006 2.5 Pin Assignments 2.5.1 Pin Map Figure 2-2 through Figure 2-5 show the C6454 pin assigments in four quadrants (A, B, C, and D). 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SYSCLK4/ AJ DV GP[5] FSX0 CLKS DR0 TINPL1 DV V TCK TMS RSV26 RSV40 V DV AJ DD33 DD33 SS SS DD33 GP[1] DR1/ AH AH V GP[4] FSR0 NMI TINPL0 TRST TDO TDI EMU17 RSV27 EMU16 EMU9 DV V SS DD33 SS GP[8] FSX1/ DX1/ AG AG CLKR
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TMS320C6454 Fixed-Point Digital Signal Processor www.ti.com SPRS311A–APRIL 2006–REVISED DECEMBER 2006 16 17 18 19 20 21 22 23 24 25 26 27 28 29 AJ V RSV77 RSV56 RSV60 V RSV61 RSV57 RSV78 V DV AED5 AED6 AED20 DV AJ SS SS SS DD33 DD33 AH V DV RSV59 RSV55 V RSV76 V V RSV58 RSV62 DV V AED14 AED2 AED18 SS AH DD33 SS S SS S DD33 SS AG V SS DVDD33 RSV48 RSV52 VSS RSV53 RSV49 DVDD33 VSS AED3 SCL AED9 AED16 AED30 AG AF AF DV RSV47 RSV51 V RSV75 V RSV54 RSV50 DV AED1 SDA AED10 AED15 AED19 DD33 SS SS DD33
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PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor www.ti.com SPRS311A–APRIL 2006–REVISED DECEMBER 2006 16 17 18 19 20 21 22 23 24 25 26 27 28 29 AEA16/ AEA15/ AEA8/ P P V CV DV V SS CV V DD RSV30 RSV31 BOOT AECLKIN DD33 SS DD SS PCI_EEAI MODE0 _SEL AEA19/ N N V V AEA7 CVDD VSS CVDD SS SS DVDD33 BOOT AHOLDA CLKIN1 AECLKIN MODE3 AEA10/ AEA9/ M M V CV V CV DV V V DV V SS DD SS DD DD33 SS SS DD33 SS MACSEL1 MACSEL0 AEA17/ AEA18/ L L CV V CV V V DV BOOT BOOT ABUSREQ ABE4 ABE5 DD SS DD
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TMS320C6454 Fixed-Point Digital Signal Processor www.ti.com SPRS311A–APRIL 2006–REVISED DECEMBER 2006 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PCBE0/ PREQ/ PINTA/ P P PTRDY PCBE3 DV V RSV05 V CV V CV DD33 SS SS DD SS DD GP[2] GP[15] GP[14] MTCLK/ N MDIO N CV V MTXD7 RSV29 RSV28 RSV04 CV V CV V DDMON SS DD SS DD SS RMREFCLK MTXD0/ M M MRXD7 MTXD6 MTXD2 MDCLK V DV CV V CV V CV SS DD33 DD SS DD SS DD RMTXD0 MTXD1/ L L MRXD4 MRXD5 MTXD4 MTXD5 DV V V CV V CV V DD33MON SS SS DD SS DD SS RMTXD1 K K DV V MCO
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PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor www.ti.com SPRS311A–APRIL 2006–REVISED DECEMBER 2006 2.6 Signal Groups Description RESETSTAT CLKIN1 Clock/PLL1 (A) RESET SYSCLK4/GP[1] and Reset and NMI PLLV1 PLL Controller Interrupts POR CLKIN2 Clock/PLL2 PLLV2 RSV02 TMS RSV03 TDO RSV04 TDI RSV05 TCK RSV06 TRST RSV07 • Reserved • IEEE Standard EMU0 1149.1 • EMU1 (JTAG) RSV76 • Emulation RSV77 • RSV78 • EMU14 EMU15 EMU16 Peripheral PCI_EN EMU17 Enable/Disable EMU18 Control/Status
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TMS320C6454 Fixed-Point Digital Signal Processor www.ti.com SPRS311A–APRIL 2006–REVISED DECEMBER 2006 TOUTL0 TINPL1 Timer 1 Timer 0 TINPL0 TOUTL1 Timers (64-Bit) (C) PREQ/GP[15] GP[7] (C) GP[6] PINTA/GP[14] (C) PRST/GP[13] GP[5] (C) GP[4] PGNT/GP[12] GPIO (B) (B) FSX1/GP[11] CLKX1/GP[3] (B) (C) FSR1/GP[10] PCBE0/GP[2] (B) (A) DX1/GP[9] SYSCLK4/GP[1] (B) (B) DR1/GP[8] CLKR1/GP[0] General-Purpose Input/Output 0 (GPIO) Port A. This pin functions as GP[1] by default. For more details, see the Device
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PRODUCT PREVIEW TMS320C6454 Fixed-Point Digital Signal Processor www.ti.com SPRS311A–APRIL 2006–REVISED DECEMBER 2006 64 Data AED[63:0] AECLKIN (A) ACE5 AECLKOUT (A) ACE4 Memory Map (A) ACE3 Space Select (A) ACE2 External Memory I/F 20 Control Address AEA[19:0] ASWE/AAWE AARDY ABE7 AR/W ABE6 AAOE/ASOE ABE5 ASADS/ASRE ABE4 Byte Enables ABE3 ABE2 ABE1 ABE0 AHOLD Bus AHOLDA Arbitration ABUSREQ Bank Address ABA[1:0] EMIFA (64-bit Data Bus) 32 DDR2CLKOUT Data DED[31:0] DDR2CLKOUT DSDCKE DSDCAS Memor
