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TMS320DM643x DMP
DSP Subsystem
Reference Guide
Literature Number: SPRU978E
March 2008
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2 SPRU978E–March 2008 Submit Documentation Feedback
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Contents Preface ............................................................................................................................... 9 1 Introduction ............................................................................................................. 11 1.1 Introduction......................................................................................................... 12 1.2 Block Diagram ..................................................................................
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5.3.2 Steps for Changing PLL2 Frequency.................................................................. 44 5.4 PLL Controller Registers ......................................................................................... 48 5.4.1 Peripheral ID Register (PID) ............................................................................ 49 5.4.2 Reset Type Status Register (RSTYPE) ............................................................... 49 5.4.3 PLL Control Register (PLLCTL) .........
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7.3.1 Module Clock ON/OFF .................................................................................. 79 7.3.2 Module Clock Frequency Scaling ...................................................................... 79 7.3.3 PLL Bypass and Power Down.......................................................................... 79 7.4 DSP Sleep Mode Management ................................................................................. 80 7.4.1 DSP Sleep Modes................................
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List of Figures 1-1 TMS320DM643x DMP Block Diagram .................................................................................. 12 2-1 TMS320C64x+ Megamodule Block Diagram........................................................................... 17 2-2 C64x+ Cache Memory Architecture...................................................................................... 19 4-1 Overall Clocking Diagram ..........................................................................................
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List of Tables 4-1 System Clock Modes and Fixed Ratios for Core Clock Domains.................................................... 30 4-2 Example PLL1 Frequencies and Dividers (27 MHZ Clock Input) .................................................... 32 4-3 Example PLL2 Frequencies (Core Voltage = 1.2V) ................................................................... 33 4-4 Example PLL2 Frequencies (Core Voltage = 1.05V).................................................................. 33 4-5 P
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8 List of Tables SPRU978E–March 2008 Submit Documentation Feedback
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Preface SPRU978E–March 2008 Read This First About This Manual This document describes the DSP subsystem in the TMS320DM643x Digital Media Processor (DMP). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. • Registers in this document are shown in figures and described in tables. – Each register figure shows a rectangle divided into fields that represent the
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TMS320C6000, C6000 are trademarks of Texas Instruments. 10 Read This First SPRU978E–March 2008 Submit Documentation Feedback
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Chapter 1 SPRU978E–March 2008 Introduction Topic .................................................................................................. Page 1.1 Introduction.............................................................................. 12 1.2 Block Diagram.......................................................................... 12 1.3 DSP Subsystem in TMS320DM643x DMP ..................................... 13 SPRU978E–March 2008 Introduction 11 Submit Documentation Feedback
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www.ti.com Introduction 1.1 Introduction The TMS320DM643x Digital Media Processor (DMP) contains a powerful DSP to efficiently handle image, video, and audio processing tasks. The DM643x DMP consists of the following primary components and sub-systems: • DSP Subsystem (DSPSS), including the C64x+ Megamodule and associated memory. • Video Processing Subsystem (VPSS), including the Video Processing Front End (VPFE) Subsystem, Image Input and Image Processing Subsystem, and the Video Processing Bac
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www.ti.com DSP Subsystem in TMS320DM643x DMP 1.3 DSP Subsystem in TMS320DM643x DMP In the DM643x DMP, the DSP subsystem is responsible for performing digital signal processing for digital media applications. In addition, the DSP subsystem acts as the overall system controller, responsible for handling many system functions such as system-level initialization, configuration, user interface, user command execution, connectivity functions, and overall system control. 1.3.1 Components of the DSP Sub
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14 Introduction SPRU978E–March 2008 Submit Documentation Feedback
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Chapter 2 SPRU978E–March 2008 TMS320C64x+ Megamodule Topic .................................................................................................. Page 2.1 Introduction.............................................................................. 16 2.2 TMS320C64x+ CPU.................................................................... 16 2.3 Memory Controllers................................................................... 18 2.4 Internal Peripherals...............................
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www.ti.com Introduction 2.1 Introduction The C64x+ Megamodule (Figure 2-1) consists of the following components: • TMS320C64x+ CPU • Internal memory controllers: – Level-1 program memory controller (L1P controller) – Level-1 data memory controller (L1D controller) – Level-2 unified memory controller (L2 controller) – External memory controller (EMC) – Internal direct memory access (IDMA) controller • Internal peripherals – Interrupt controller (INTC) – Power-down controller (PDC) 2.2 TMS320C64x+
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www.ti.com TMS320C64x+ CPU • Protected mode operation: a two-level system of privileged program execution to support higher capability operating systems and system features, such as memory protection • Exceptions support for error detection and program redirection to provide robust code execution • Hardware support for modulo loop operation to reduce code size • Industry's first assembly optimizer for rapid development and improved parallelization Figure 2-1. TMS320C64x+ Megamodule Block Diagram
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www.ti.com Memory Controllers 2.3 Memory Controllers The C64x+ Megamodule implements a two-level internal cache-based memory architecture with external memory support. Level 1 memory is split into separate program memory (L1P memory) and data memory (L1D memory). Figure 2-2 shows a diagram of the memory architecture. L1P and L1D are configurable as part L1 RAM (normal addressable on-chip memory) and part L1 cache. L1 memory is accessible to the CPU without stalls. Level 2 memory (L2) can also be
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www.ti.com Memory Controllers Figure 2-2. C64x+ Cache Memory Architecture C64x+ CPU Fetch Path Data Path 2 x 64 bit L1D L1D Write L1P L1P SRAM Cache Buffer SRAM Cache L1 Data L1 Program L2 Cache L2 SRAM L2 Unified Data/Program Memory External Memory Legend: addressable memory cache memory data paths managed by cache controller SPRU978E–March 2008 TMS320C64x+ Megamodule 19 Submit Documentation Feedback 256 bit 256 bit 64 bit 256 bit 256 bit 128 bit
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www.ti.com Memory Controllers 2.3.2 L1D Controller The L1D controller is the hardware interface between level 1 data memory (L1D memory) and the other components in the C64x+ Megamodule (for example, C64x+ CPU, L2 controller, and EMC). The L1D controller responds to data requests from the C64x+ CPU and manages transfer operations between L1D memory and the L2 controller and between L1D memory and the EMC. Refer to the device-specific data manual for the amount of L1D memory on the device. The L1
