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Intel® Xeon® Processor E5-1600/
E5-2600/E5-4600 Product Families
Datasheet - Volume One
May 2012
Reference Number: 326508, Revision: 002
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U S IN A NFORMA L LE E S AND/ S O TT ION O HERW R U IN S T E IS O H E IS FA I G D NREED O TE CU L P MEN IN RO D W TU IS RC IT T PROV IN S IG N C B ID L YU IN ED DIT IN N EG L L CON , T IH ABI E IN NE LCT IT TY E ION LO PROD R W WIA TR U HR C Inte AN TS TA l® IR ES E N PROD RE OL TA D U TC IENG T SS I. G T N N O O ED F LI IT N C N O EE R N SS IN S E, F T Ex O ER Np A D rED eP sA s FOR * R O TIC R A U IMPL N LAR Y A P IED PPL UR ,ICA B PO YS E TE IO S , M T N O IN E PPEL RC W H OR H AICH T NT O AB
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Contents 1Overview................................................................................................................. 13 1.1 Introduction ..................................................................................................... 13 1.1.1 Processor Feature Details ........................................................................ 14 1.1.2 Supported Technologies .......................................................................... 14 1.2 Interfaces .............
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3.2.4 Execute Disable Bit .................................................................................83 3.3 Intel® Hyper-Threading Technology.....................................................................83 3.4 Intel® Turbo Boost Technology ...........................................................................83 3.4.1 Intel® Turbo Boost Operating Frequency ...................................................83 3.5 Enhanced Intel SpeedStep® Technology..............................
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7 Electrical Specifications......................................................................................... 151 7.1 Processor Signaling ......................................................................................... 151 7.1.1 System Memory Interface Signal Groups ................................................. 151 7.1.2 PCI Express* Signals ............................................................................ 151 7.1.3 DMI2/PCI Express* Signals........................
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Figures 1-1 Intel® Xeon® Processor E5-2600 Product Family on the 2 Socket Platform ...........................................................................................................14 1-2 PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2)...................17 2-1 PCI Express* Layering Diagram ...........................................................................26 2-2 Packet Flow through the Layers ...............................................................
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2-47 RdPCIConfigLocal()............................................................................................ 66 2-48 WrPCIConfigLocal() ........................................................................................... 68 2-49 The Processor PECI Power-up Timeline() .............................................................. 70 2-50 Temperature Sensor Data Format........................................................................ 76 4-1 Idle Power Management Breakdown of th
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10-1 STS200C Passive/Active Combination Heat Sink (with Removable Fan) ...................244 10-2 STS200C Passive/Active Combination Heat Sink (with Fan Removed)......................244 10-3 STS200P and STS200PNRW 25.5 mm Tall Passive Heat Sinks ................................245 10-4 Boxed Processor Motherboard Keepout Zones (1 of 4) ..........................................246 10-5 Boxed Processor Motherboard Keepout Zones (2 of 4) ..........................................247 10-6 Boxed P
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4-10 Package C-State Power Specifications .................................................................. 97 5-1 Processor SKU Summary Table ......................................................................... 104 5-2 Tcase: 8-Core 150W Thermal Specifications, Workstation Platform SKU Only........... 104 5-3 8-Core 150W Thermal Profile, Workstation Platform SKU Only ............................. 106 5-4 Tcase: 8-Core 135W Thermal Specifications 2U ........................................
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7-8 Fault Resilient Booting (Output Tri-State) Signals.................................................163 7-9 Processor Absolute Minimum and Maximum Ratings .............................................164 7-10 Storage Condition Ratings.................................................................................165 7-11 Voltage Specification........................................................................................167 7-12 Processor Current Specifications ......................
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Revision History Revision Description Revision Date Number 001 Initial Release March 2012 002 Added Intel® Xeon® Processor E5-4600 Product Family May 2012 § Intel® Xeon® Processor E5-1600/ E5-2600/E5-4600 Product Families 11 Datasheet Volume One
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12 Intel® Xeon® Processor E5-1600/ E5-2600/E5-4600 Product Families Datasheet Volume One
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Overview 1 Overview 1.1 Introduction The Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet - Volume One provides DC specifications, signal integrity, differential signaling specifications, land and signal definitions, and an overview of additional processor feature interfaces. The Intel® Xeon® processor E5-1600/E5-2600/E5-4600 product families are the next generation of 64-bit, multi-core enterprise processors built on 32-nanometer process technology. Throughout this
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Overview Figure 1-1. Intel® Xeon® Processor E5-2600 Product Family on the 2 Socket Platform Figure 1-2. Intel® Xeon® Processor E5-4600 Product Family on the 4 Socket Platform 1.1.1 Processor Feature Details • Up to 8 execution cores • Each core supports two threads (Intel® Hyper-Threading Technology), up to 16 threads per socket 14 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families Datasheet Volume One
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Overview • 46-bit physical addressing and 48-bit virtual addressing • 1 GB large page support for server applications • A 32-KB instruction and 32-KB data first-level cache (L1) for each core • A 256-KB shared instruction/data mid-level (L2) cache for each core • Up to 20 MB last level cache (LLC): up to 2.5 MB per core instruction/data last level cache (LLC), shared among all cores • The Intel® Xeon® processor E5-4600 product family supports Directory Mode, Route Through, and Node IDs to redu
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Overview — UDIMMs x8, x16 — RDIMMs x4, x8 — LRDIMM x4, x8 (2-Gb and 4-Gb only) • Up to 8 ranks supported per memory channel, 1, 2 or 4 ranks per DIMM • Open with adaptive idle page close timer or closed page policy • Per channel memory test and initialization engine can initialize DRAM to all logical zeros with valid ECC (with or without data scrambler) or a predefined test pattern • Isochronous access support for Quality of Service (QoS), native 1 and 2 socket platforms - Intel® Xeon® process
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Overview — x16 port (Port 2 & Port 3) may negotiate down to x8, x4, x2, or x1. — x8 port (Port 1) may negotiate down to x4, x2, or x1. — x4 port (Port 0) may negotiate down to x2, or x1. — When negotiating down to narrower widths, there are caveats as to how lane reversal is supported. • Non-Transparent Bridge (NTB) is supported by PCIe* Port3a/IOU1. For more details on NTB mode operation refer to PCI Express Base Specification - Revision 3.0: — x4 or x8 widths and at PCIe* 1.0, 2.0, 3.0 sp
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Overview Figure 1-3. PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2) Port 1 Port 2 Port 3 Port 0 (IOU2) (IOU0) (IOU1) DMI / PCIe PCIe PCIe PCIe Transaction Transaction Transaction Transaction Link Link Link Link Physical Physical Physical Physical 0…3 0…3 4…7 0…3 4…7 8…11 12..15 0…3 4…7 8…11 12..15 X4 X4 X4 X4 X4 X4 X4 X4 X4 X4 X4 DMI Port 1a Port 1b Port 2a Port 2b Port 2c Port 2d Port 3a Port 3b Port 3c Port 3d X8 X8 X8 X8 X8 Port 1a Port 2a Port 2c Port 3a Port 3c X16
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Overview • Home snoop based coherency •3-bit Node ID • 46-bit physical addressing support • No Intel QuickPath Interconnect bifurcation support • Differential signaling • Forwarded clocking • Up to 8.0 GT/s data rate (up to 16 GB/s direction peak bandwidth per port) — All ports run at same operational frequency — Reference Clock is 100 MHz — Slow boot speed initialization at 50 MT/s • Common reference clocking (same clock generator for both sender and receiver) • Intel® Interconnect Built-In-Se
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Overview • Memory thermal monitoring via MEM_HOT_C01_N and MEM_HOT_C23_N Signals 1.3.4 PCI Express • L0s is not supported • L1 ASPM power management capability 1.3.5 Intel QuickPath Interconnect • L0s is not supported • L0p and L1 power management capabilities 1.4 Thermal Management Support • Digital Thermal Sensor with multiple on-die temperature zones • Adaptive Thermal Monitor • THERMTRIP_N and PROCHOT_N signal support • On-Demand mode clock modulation • Open and Closed Loop Thermal Throttlin
