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® TM
Intel Core 2 Duo processor
®
and Mobile Intel GME965
Express Chipset
Development Kit User Manual
June 2007
Document Number: 316704-001
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNES
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Contents 1 About This Manual ............................................................................................6 1.1 Content Overview...................................................................................6 1.2 Text Conventions ...................................................................................6 1.3 Glossary of Terms and Acronyms..............................................................8 1.4 Support Options....................................
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Figures Figure 1. Development Board Block Diagram.......................................................24 Figure 2. Development Board Component Locations.............................................39 Figure 3. Back Panel Connector Locations...........................................................42 Figure 4. D-Connector to Component Video Cable................................................43 Figure 5. D-Connector to Composite Video Cable .......................................
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Revision History Document Revision Description Revision Date Number Number 316704 001 Initial public release. June 2007 § 316704-001 / Development Kit User’s Manual 5
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About This Manual 1 About This Manual ® TM This user’s manual describes the use of the Intel Core 2 Duo processor and Mobile ® Intel GME965 Express Chipset development kit. This manual has been written for OEMs, system evaluators, and embedded system developers. This document defines all jumpers, headers, LED functions, and their locations on the development board, along with subsystem features and POST codes. This manual assumes basic familiarity in the fundamental concepts involve
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About This Manual Table 1. Text Conventions Notation Definition # The pound symbol (#) appended to a signal name indicates that the signal is active low. (e.g., PRSNT1#) Variables Variables are shown in italics. Variables must be replaced with correct values. Instructions Instruction mnemonics are shown in uppercase. When you are programming, instructions are not case-sensitive. You may use either uppercase or lowercase. Numbers Hexadecimal numbers are represented by a string of
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About This Manual 1.3 Glossary of Terms and Acronyms Table 2 defines conventions and terminology used throughout this document. Table 2. Terms and Acronyms Term/Acronym Definition Aggressor A network that transmits a coupled signal to another network. Anti-etch Any plane-split, void or cutout in a VCC or GND plane. Assisted Gunning The front-side bus uses a bus technology called AGTL+, or Assisted Transceiver Logic+ Gunning Transceiver Logic. AGTL+ buffers are open-drain, and requi
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About This Manual Term/Acronym Definition manufacturer’s conditions required for AC timing specifications; i.e., ringback, etc.) and the output pin of the driving agent crossing the switching voltage when the driver is driving a test load used to specify the driver’s AC timings. Maximum and Minimum Flight Time - Flight time variations are caused by many different parameters. The more obvious causes include variation of the board dielectric constant, changes in load condition, cross
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About This Manual Term/Acronym Definition System Bus The System Bus is the microprocessor bus of the processor. Setup Window The time between the beginning of Setup to Clock (TSU_MIN) and the arrival of a valid clock edge. This window may be different for each type of bus agent in the system. Simultaneous Simultaneous Switching Output (SSO) effects are differences in electrical Switching Output timing parameters and degradation in signal quality caused by multiple signal outputs si
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About This Manual Acronym Definition BIOS Basic Input/Output System CK-SSCD Spread Spectrum Differential Clock CMC Common Mode Choke CMOS Complementary Metal-Oxide-Semiconductor CPU Central Processing Unit (processor) DDR Double Data Rate DMI Direct Memory Interface ECC Error Correcting Code EEPROM Electrically Erasable Programmable Read-Only Memory EHCI Enhanced Host Controller Interface EMA Extended Media Access EMI Electro Magnetic Interference ESD Electrostatic Discharge
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About This Manual Acronym Definition LOM LAN on Motherboard LPC Low Pin Count LS Low-speed. Refers to USB LVDS Low Voltage Differential Signaling mBGA Mini Ball Grid Array MC Modem Codec MEC Media Expansion Card MHz Mega-Hertz OEM Original Equipment Manufacturer PCIe PCI Express* PCM Pulse Code Modulation POST Power On Self Test PLC Platform LAN Connect RAID Redundant Array of Inexpensive Disks RTC Real Time Clock SATA Serial ATA SIO Super Input/Output SKU StockKeeping U
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About This Manual Acronym Definition VREG Voltage Regulator XDP eXtended Debug Port 1.4 Support Options 1.4.1 Electronic Support Systems Intel’s web site (http://www.intel.com/) provides up-to-date technical information and product support. This information is available 24 hours per day, 7 days per week, providing technical information whenever you need it. 1.4.2 Additional Technical Support If you require additional technical support, please contact your Intel Representative o
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About This Manual Intel Literature Fulfilment Center P.O. Box 5937 Denver, Colorado 80217-9808 USA Email a request to: intelsupport@hibbertgroup.com Please make sure to include in your mailed/emailed request: SKU # Company Name Your Name (first, last) Full mailing address Daytime Phone Number in case of questions Note: Please be aware not all documents are available in all media types. Some may only be available as a download. 1.6 Related Documents Table 5 provides a summar
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Getting Started 2 Getting Started This chapter identifies the development kit’s key components, features and specifications. It also details basic development board setup and operation. 2.1 Overview ® TM The development board consists of a baseboard populated with the Intel Core 2 ® Duo processor, the Mobile Intel GME965 Express Chipset, other system board components and peripheral connectors. Note: The development board is shipped as an open system allowing for maximum flexibility
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Getting Started Development Board Comments Implementation Three x1 connectors Revision 1.1 compliant F One x16 connector There are Five x1 PCI Express* slots but PCI Express* slots 2 and 4 are not intended for use with E PCI Express* add-in cards. Only slots 1, 3 and 5 are supported. A 10/100/1000 Mbps connectivity The 82566MM is connected to the ICH via T ® On-Board LAN from the Intel 82566MM Gigabit the ICH’s GLCI and LCI interfaces. U Platform LAN Connect component R
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Getting Started Development Board Comments Implementation ACPI Compliant S0 – Power On S3 – Suspend to RAM S4 – Suspend to Disk Power S5 – Soft Off Management M0 – All Wells powered M1 – Main Well down. Only ME power on M-off – ME powered off Form Factor ATX 2.2 like form factor 10 layer board – 12” x 10.2” Note: Review the document provided with the Development Kit titled “Important Safety and Regulatory Information”. This document contains safety warnings and cautions th
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Getting Started Note: While every care was taken to ensure the latest versions of drivers were provided on the enclosed CD at time of publication, newer revisions may be available. Updated drivers for Intel components can be found at: http://developer.intel.com/design/intarch/software/index.htm For all third-party components, please contact the appropriate vendor for updated drivers. Note: Software in the kit is provided free by the vendor and is only licensed for evaluation purpos
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Getting Started VGA Monitor: Any standard VGA or multi-resolution monitor may be used. The setup instructions in this chapter assume the use of a standard VGA monitor, TV, or flat panel monitor. Keyboard: The development board can support either a PS/2 or USB style keyboard. Mouse: The development board can support either a PS/2 or USB style mouse. Hard Drives and Optical Disc Drives: Up to Three SATA drives and two IDE devices (master and slave) may be connected to the development
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Getting Started Other Devices and Adapters: The development board functions much like a standard desktop computer motherboard. Most PC-compatible peripherals can be attached and configured to work with the development board. 2.5 Setting Up the Development Board Once the necessary hardware (described in Section 2.4) has been gathered, follow the steps below to set up the development board. Note: To locate items discussed in the procedure below, please refer to Chapter 4. 1. Crea
