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Intel® 41110 Serial to Parallel PCI
Bridge
Design Guide
March 2006
Order Number: 310335-001
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® INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
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Contents Contents 1 About This Document ...................................................................................................................7 1.1 Terminology and Definitions .................................................................................................7 2 Introduction....................................................................................................................................9 2.1 PCI Express Interface Features..............................
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Contents 10.2 41110 Reference and Compensation Pins.........................................................................48 11 41110 Customer Reference Boards...........................................................................................51 11.1 Board Stack-up...................................................................................................................51 11.2 Material...............................................................................................
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Contents 10 Embedded PCI-X 133 MHz Routing Recommendations............................................................36 11 Embedded PCI-X 100 MHz Routing Recommendations............................................................37 12 PCI-X 66 MHz Embedded Routing Recommendations..............................................................38 13 PCI 66 MHz Embedded Table....................................................................................................39 14 PCI 33 MHz Embedded
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Contents Revision History Date Revision Description March 2006 001 Initial release. vi Intel® 41110 Serial to Parallel PCI Bridge Design Guide
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About This Document 1 This document provides layout information and guidelines for designing platform or add-in board applications with the Intel® 41110 Serial to Parallel PCI Bridge (also called the 41110 Bridge). It is recommended that this document be used as a guideline. Intel recommends employing best-known design practices with board level simulation, signal integrity testing and validation for a robust design. Designers should note that this guide focuses upon specific design consider
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About This Document Table 1. Terminology and Definitions (Sheet 2 of 2) Term Definition Printed circuit board. Layer 1: copper Example manufacturing process consists of Prepreg the following steps: Layer 2: GND • Consists of alternating layers of core and prepreg stacked Core • The finished PCB is heated and cured. PCB Layer 3: VCC15 Prepreg • The via holes are drilled Layer 4: copper • Plating covers holes and outer surfaces • Etching removes unwanted copper • Board is tinned, coated with s
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Introduction 2 The Intel® 41110 Serial to Parallel PCI Bridge integrates a PCI Express-to-PCI bridge. The bridge follows the PCI-to-PCI Bridge programming model. The PCI Express port is compliant to the PCI Express Specification, Revision 1.0. The PCI bus interface is fully compliant to the PCI Local Bus Specification, Revision 2.3. 2.1 PCI Express Interface Features • PCI Express Specification, Revision 1.0b compliant. • Support for single x8, single x4 or single x1 PCI Express operation. •
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Introduction • Up to two downstream delayed (memory read, I/O read/write and configuration read/write) transaction. • Tunable inbound read prefetch algorithm for PCI MRM/MRL commands • Local initialization via SMBus • Secondary side initialization via Type 0 configuration cycles. 2.3 Power Management • Support for PCI Express Active State Power Management (ASPM) L0s link state • Support for PCI PM 1.1 compatible D0, D3hot and D3cold device power states • Support for PME# event propagation on be
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Introduction Figure 1. Microcontroller Block Diagram Serial to Parallel PCI Bridge 2.4.2 Microcontroller Connections to the 41110 Figure 2 shows the SMB interface from the 41110 to the microcontroller. Intel® 41110 Serial to Parallel PCI Bridge Design Guide 11
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Introduction Figure 2. 41110 Microcontroller Connections Serial to Parallel PCI Bridge 2.5 JTAG • Compliant with IEEE Standard Test Access Port and Boundary Scan Architecture 1149.1a 2.6 Related Documents • . • PCI Express Specification, Revision 1.0, from www.pci-sig.com. • PCI Express Design Guide, Revision 0.5 • PCI Local Bus Specification, Revision 2.3, from www.pci-sig.com. • PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a, from www.pci-sig.com. • IEEE Standard Test Acces
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Introduction Figure 3. 41110 Block Diagram Serial to Parallel PCI Bridge 2.7 Intel® 41110 Serial to Parallel PCI Bridge Applications This section provides a block diagram for a typical the 41110 application. This application shows a PCI-E adapter card with two Dual 2Gb Fibre Channel controllers. Each of the PCI-X bus segments is connected to the Dual 2Gb Fibre Channel chip running at 133MHz. The two Dual FC chips provides the four 2Gb/s outputs. Intel® 41110 Serial to Parallel PCI Bridge De
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Introduction Figure 4. 41110 Adapter Card Block Diagram Serial to Parallel PCI Bridge 14 Intel® 41110 Serial to Parallel PCI Bridge Design Guide
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Package Information 3 3.1 Package Specification The 41110 Bridge is in a 567-ball FCBGA package, 31mm X 31mm in size, with a 1.27mm ball pitch (see Figure 5 and Figure 6). Figure 5. 41110 Bridge Package Dimensions (Top View) Die Handling Keepout 0. 491 in. Exclusion Area Area 0. 291 in. 0. 247 in. 17 . 00 mm 21 . 00 mm 31 . 00 mm 0. 547 in. 0. 200 in. 17. 00 mm 21 . 00 mm 31 . 00 mm Intel® 41110 Serial to Parallel PCI Bridge Design Guide 15
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Package Information Figure 6. 41110 Bridge Package Dimensions (Side View) 0.84±0.05 mm Substrate 2.445±0.102 mm Decoup Die Cap 2.010±0.099 mm 0.7 mm Max 0.20 See Note 4. -C- 0.20 Seating Plane 0.435±0.025 mm See Note 3 See Note 1 Notes: 1. Primary datum -C- and seating plan are defined by the spherical crowns of the solder balls (shown before motherboard attach). 2. All dimensions and tolerances conform to ANSI Y14.5M-1994 3. BGA has a pre-SMT height of 0.5 mm and post-SMT height of 0.41-0.46 mm
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Power Plane Layout 4 This chapter provides details on the decoupling and voltage planes needed to bias the 41110 package. 4.1 41110 Decoupling Guidelines Table 2 lists the decoupling guidelines for the 41110. Figure 7 and Figure 8 provide the decoupling capacitors around the 41110 ball grid pins. Figure 7. Decoupling Placement for Core and PCI Express Voltage Planes B2713-01 Intel® 41110 Serial to Parallel PCI Bridge Design Guide 17
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Power Plane Layout Figure 8. Decoupling Placement for PCI/PCI-X 1.5V and 3.3V Voltage Planes Capacitor Legend 0603-0.1 F 0603-1 F 1206-10 F B2714-01 18 Intel® 41110 Serial to Parallel PCI Bridge Design Guide
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Power Plane Layout Table 2. 41110 Decoupling Guidelines 41110 C ESR ESL # of Voltage Plane Voltage Bridge Package Location (uF) (mΩ ) (nH) Caps Pins PCI/PCI-X 50- 1.0- Beneath 41110 3.3V VCC33 0.1 0603 5 Voltage 300 3.0 Bridge BGA As close as design PCI/PCI-X 50- 1.0- 3.3V VCC33 1.0 0603 2 rules will allow to Voltage 300 3.0 41110 Bridge BGA As close as design PCI/PCI-X 50- 1.0- 3.3V VCC33 10 1206 3 rules will allow to Voltage 300 3.0 41110 Bridge BGA Beneath 41110 Core Voltage 1.5V VCC1
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Power Plane Layout Note: Linear voltage regulators are recommended when using 1.5 Volt power supplies. Figure 9. 41110 Bridge Single-Layer Split Voltage Plane re Core PCI Express B2715-01 20 Intel® 41110 Serial to Parallel PCI Bridge Design Guide
