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CLC-CAPT-PCASM
Data Capture Board User’s Guide
May 1999
Rev 1.0.0
N
CLC-CAPT-PCASM
Data Capture Board User’s Guide
Section I. Introduction Table of Contents
The CLC3790093 Data Capture Board enables simple evaluation I. Introduction
of National Semiconductor’s High Speed Analog to Digital Con- II. Capturing Data from ADC
verters (ADCs) and the Diversity Receiver Chip Set (DRCS). The Evaluation Boards
Data Capture Board interfaces the outputs of these devices to the III. Capturing
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BPF 8. Clock Source. If you wish to test the ADC with a fixed clock frequency, you may install a standard TTL FILTERED SIGNAL oscillator in the socket provided on the evaluation SOURCE OPTIONAL board. Otherwise, you will need to provide a low CLOCK SOURCE phase noise sinewave or square wave clock source +5V at the appropriate SMA connector on the evaluation VCC CLK VCC Clock board. An amplitude of 10 to 16dBm is recommended. (2A) 10-16dBm Optional GND TTL Data Here, again, the HP
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complement number can be converted to offset binary by inverting the MSB. This is the first step in the Matlab FIFO 18-bits routine for FFT analysis. 32k depth UART RDY2 CLC5956 Data WCLK Clock Analog Input Condition Offset Binary Number Two's Complement ASCII Value Stored Ain- >> Ain - Full Scale 0000 0000 0000 1000 0000 0000 2048 J9 Ain- > Ain - Mid Scale 0111 1111 1111 1111 1111 1111 4095 Data 9-pin Ain > Ain- + Mid Scale 1000 0000 0000 0000 0000 0000 0 FPGA 12-18 Ser
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SMA Connectors When you run capture.exe, you will see the following The output clock SMA connector provides a signal that window pop up onto your PC: can be used to phase lock a signal source. The frequency is that of the input clock signal divided by 2. For example, with an attached CLC5958 ADC evaluation board at 52MSPS the clock output signal will be a 26MHz square wave. The second SMA connector is currently unused. This is the data capture control
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Verify the connections and, if necessary, try the other “Default” and then on “OK”. If you do not have a COM port. (Note that you must have a clock applied to C:\temp directory, please make one. The reason for this the ADC Evaluation board during this communication is that the Matlab script files for data analysis look auto- verification stage. Check to make sure that either an matically for the file C:\temp\data.dat. If you wish to external clock or the TTL oscillator i
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To look at the data that you have just captured, left click on the “Plot_Data” button. If you have collected data with a 12-bit ADC at 52MSPS and a -2dBFS sinewave input at 5MHz, you will see two’s complement data that looks like this: Select “Histogram Debug”, as shown above, and click on “OK”. When the data capture control panel returns, you can verify your capture settings by positioning the mouse over the progress bar. You will see the following display: Next, left click on th
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In this example, we have captured data from a 12-Bit Getting Started ADC. Remember that the data that we are plotting is the To use the Data Capture board to capture data from bin count information. The ADC output codes that were National’s DRCS Evaluation Board, you will need the fol- exercised ranged from code 236 to code 3865. The maxi- lowing hardware, software, and documentation. Several mum count was set to 16384 (with DIP switches 4 and 5 analysis tools are provided in t
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24-bit words via the serial port as 96K bytes. Each word Using the DATA CAPTURE Control Panel is interpreted as a 24-bit two’s complement integer and The Data Capture Program, “capture.exe”, must be stored as 32K ASCII words in a user defined file. Each copied into a directory on the user’s PC. The setup/install value is terminated with a carriage return (hexadecimal program on the CDROM automatically places this 0D). When a Diversity Receiver Evaluation Bo
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The “Configure I/O” button opens the user port option The “Configure Capture” button invokes the user dialog menu window. Clicking the left mouse button selects the window for the remainder of the configuration options. desired port (the default Windows address and IRQ is After selecting the desired options, a left mouse click on assumed). Clicking the “OK” button sends an identifica- “OK” stores the configuration variables and returns to tion command out the selected port and listens for the the Con
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#4 & #5 as indicated in the Histogram Max Target gram data of the DRCS output generated by the table. Due to a high data resolution and relatively Capture Board at an input frequency of 150MHz and slow data rate, a relatively long period of time is 16dBm in amplitude using all the default DRCS set- required for generating histogram data from the tings. The data source was the DDC serial output DRCS with high decimation values in the DDC. (Capture Histogram mode was used where Under some circumst
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** From the Windows Start Programs menu, launch the Capture program (it’s inside the C:\nsc folder). Right click inside the Control Panel and select Configure I/O and click the appropriate PC COM port button. Next, right click inside the Control Panel and select Configure Capture. Select the following options: Mode = Capture; Bits =24; Channel = A; From = AOUT; 1st Bit = Capture 1st Bit; Phase = In Phase Only. Click “OK” and then click the Start button in the Control Panel to start the data captur
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** DRCS_Serial “DRCS_ser_fft.m” is the script ** 12-bit FFT “b12_FFT.m” is the script intended for intended for analysis of the DRCS 24-bit serial out- data analysis in conjunction with the CLC5956 put data. Fsample is set to a default of 52e6/192 Evaluation Boards. which is the GSM standard output rate of ** DNL_INL “dnl_inl.m” - is the script intended for data 270.833KS/s. The “search’ option is enabled; analysis of the histogram data file generated by the therefore, excluding the DC bins, the
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CLC-CAPT-PCASM Evaluation Board - Layer 1 CLC-CAPT-PCASM Evaluation Board - Layer 2 CLC-CAPT-PCASM Evaluation Board - Layer 3 CLC-CAPT-PCASM Evaluation Board - Layer 4 13 http://www.national.com
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