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CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
72-Mbit (2M x 36/4M x 18/1M x 72)
Pipelined SRAM with NoBL™ Architecture
Features Functional Description
■ Pin-compatible and functionally equivalent to ZBT™ The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25
are 2.5V, 2M x 36/4M x 18/1M x 72 synchronous pipelined burst
■ Supports 250 MHz bus operations with zero wait states
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.
❐ Available speed grades are 250, 200, and 167 MHz
They are designed to support
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CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Logic Block Diagram – CY7C1470BV25 (2M x 36) ADDRESS A0, A1, A REGISTER 0 A1 A1' D1 Q1 A0 BURST A0' D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O S U D U E T A T P N P U T U S T ADV/LD A T WRITE REGISTRY E R MEMORY AND DATA COHERENCY B BW a WRITE E S DQ s ARRAY CONTROL LOGIC G U DRIVERS T DQ Pa BW b A I F E DQ Pb BW c M S F BW d DQ Pc T E P E E R R DQ Pd S WE R S I S E N E G INPUT INPUT REGISTER 1 E REGISTER 0 E
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CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Logic Block Diagram – CY7C1474BV25 (1M x 72) ADDRESS A0, A1, A REGISTER 0 A1 A1' D1 Q1 A0 BURST A0' D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O U U T T P S D P U E U ADV/LD A T N T T WRITE REGISTRY S BW a A R MEMORY E B AND DATA COHERENCY WRITE E DQ s BW b U ARRAY S CONTROL LOGIC G DRIVERS A F DQ Pa BW c T I M E F BW d S DQ Pb P E E T S R R BW e DQ Pc E S I R DQ Pd BW f N S G BW g DQ Pe E E BW h DQ Pf DQ Pg DQ
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CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Pin Configurations Figure 1. 100-Pin TQFP Pinout DQPc 1 NC 1 DQPb A 80 80 DQc 2 NC 2 DQb NC 79 79 DQc 3 DQb NC 3 NC 78 78 V 4 V DDQ 4 V DDQ 77 V DDQ 77 DDQ V 5 V V 5 SS SS V 76 SS SS 76 DQc 6 NC 6 DQb NC 75 75 DQc 7 DQb NC 7 DQPa 74 74 DQc 8 DQb DQb 8 DQa 73 73 DQc 9 DQb DQb 9 DQa 72 72 V V SS 10 V SS 10 V 71 SS 71 SS V V DDQ DDQ 11 V 11 V 70 DDQ 70 DDQ DQc 12 DQb DQb 12 DQa 69 69 DQc 13 DQb DQb 13 DQa 68 68 NC NC 14 V 14 V 67 SS 67 SS V DD V 15 NC
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CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Pin Configurations (continued) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1470BV25 (2M x 36) 1 23 4 5 6 7 89 10 11 A NC/576M A CE BW BW CE ADV/LD A A NC CEN 1 c b 3 B NC/1G A CE2 BW BW CLK WE OE A A NC d a DQP NC V V V V V V V NC DQP C c DDQ SS SS SS DDQ b SS SS D DQ DQ V V V V V V V DQ DQ c c DDQ DD SS SS SS DD DDQ b b E DQ DQ V V V V V V V DQ DQ c c DDQ DD SS SS SS DD DDQ b b DQ DQ V V V V V V V DQ DQ F c c DDQ DD SS SS SS DD DDQ b b DQ DQ V V V V V
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CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Pin Configurations (continued) 209-Ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1474BV25 (1M × 72) 12 3 4 5 6 7 8 9 10 11 DQg DQgAA CE ADV/LDA CEA DQb DQb A 2 3 DQg DQg BWS BWS NC WE A BWS BWS DQb DQb B c g b f C DQg DQg BWS BWS NC/576M CE NC BWS BWS DQb DQb h d 1 e a DQg DQg V NC NC/1G OE NC NC V DQb DQb D SS SS E DQPg DQPc V V V V V V V DDQ DDQ DD DD DD DDQ DDQ DQPf DQPb DQc F DQc V V V NC V V DQf V SS SS SS SS SS DQf SS G DQc DQc V V V V V V DDQ DDQ NC DD
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CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Table 1. Pin Definitions Pin Name IO Type Pin Description A0 Input- Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the A1 Synchronous CLK. A BW Input- Byte Write Select Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled a BW Synchronous on the rising edge of CLK. BW controls DQ and DQP , BW controls DQ and DQP , BW controls b a a a b b b c BW DQ and DQP , BW controls DQ and DQP , BW c
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CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Table 1. Pin Definitions (continued) Pin Name IO Type Pin Description TMS Test Mode Select TMS Pin Controls the Test Access Port State Machine. Sampled on the rising edge of TCK. Synchronous TCK JTAG Clock Clock Input to the JTAG Circuitry. Power Supply Power Supply Inputs to the Core of the Device. V DD IO Power Supply Power Supply for the IO Circuitry. V DDQ Ground Ground for the Device. Must be connected to ground of the system. V SS NC – No Connect
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CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 access (read, write, or deselect) is latched into the Address on page 8. When ADV/LD is driven HIGH on the subsequent Register (provided the appropriate control signals are asserted). clock rise, the Chip Enables (CE , CE , and CE ) and WE inputs 1 2 3 are ignored and the burst counter is incremented. The correct and DQP On the next clock rise the data presented to DQ BW (BW for CY7C1470BV25, BW for CY7C1472BV25, a,b,c,d a,b (DQ /DQP for CY7C1470BV25, DQ
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CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Table 4. Truth Table [1, 2, 3, 4, 5, 6, 7] The truth table for CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 follows. Address Operation CE ZZ ADV/LD WE BW OE CEN CLK DQ x Used Deselect Cycle None H L L X X X L L-H Tri-State Continue Deselect Cycle None X L H X X X L L-H Tri-State Read Cycle External L L L H X L L L-H Data Out (Q) (Begin Burst) Read Cycle Next X L H X X L L L-H Data Out (Q) (Continue Burst) NOP/Dummy Read External L L L H X H L L-H Tri-Sta
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CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Table 5. Partial Write Cycle Description [1, 2, 3, 8] The partial write cycle description for CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 follows. Function (CY7C1470BV25) WE BW BW BW BW d c b a Read H X X X X Write – No bytes written L H H H H Write Byte a – (DQ and DQP) L HHH L a a Write Byte b – (DQ and DQP)LHHLH b b Write Bytes b, a L H H L L Write Byte c – (DQ and DQP)LHLHH c c Write Bytes c, a L H L H L Write Bytes c, b L H LL L H Write Bytes c, b
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CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Test MODE SELECT (TMS) IEEE 1149.1 Serial Boundary Scan (JTAG) The TMS input is used to give commands to the TAP controller The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 and is sampled on the rising edge of TCK. It is allowable to leave incorporates a serial boundary scan test access port (TAP). This this ball unconnected if the TAP is not used. The ball is pulled up port operates in accordance with IEEE Standard 1149.1-1990 internally, resulting in a l
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CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Instruction Register Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and Three-bit instructions can be serially loaded into the instruction TDO. During this state, instructions are shifted through the register. This register is loaded when it is placed between the TDI instruction register through the TDI and TDO balls. To execute and TDO balls as shown in the “TAP Controller Bloc
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CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 possible to capture all other signals and simply ignore the value BYPASS of the CLK captured in the boundary scan register. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary placed between the TDI and TDO balls. The advantage of the scan regist
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CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 TAP AC Switching Characteristics [9, 10] Over the Operating Range Parameter Description Min Max Unit Clock t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH time 20 ns TH t TCK Clock LOW time 20 ns TL Output Times t TCK Clock LOW to TDO Valid 10 ns TDOV t TCK Clock LOW to TDO Invalid 0 ns TDOX Setup Times t TMS Setup to TCK Clock Rise 5 ns TMSS t TDI Setup to TCK Clock Rise 5 ns TDIS t Capture Setup to TCK Rise 5 ns CS Ho
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CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Figure 5. 2.5V TAP AC Output Load Equivalent 2.5V TAP AC Test Conditions 1.25V Input pulse levels.................................................V to 2.5V SS Input rise and fall time .....................................................1 ns 50Ω Input timing reference levels......................................... 1.25V Output reference levels ................................................ 1.25V TDO Test load termination supply voltage ................
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CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Table 8. Identification Codes Instruction Code Description EXTEST 000 Captures IO ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures IO ring contents. Places the boundary scan register
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CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Boundary Scan Exit Order (4M x 18) Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID 1 D214 R427 L10 40 B10 2 E215 P628 K10 41 A8 3F2 16 R6 29 J10 42 B8 4G2 17 R8 30 H11 43 A7 5J1 18 P3 31 G11 44 B7 6 K119 P432 F11 45 B6 7L1 20 P8 33 E11 46 A6 8M1 21 P9 34 D11 47 B5 9 N1 22 P10 35 C11 48 A4 10 R1 23 R9 36 A11 49 B3 11 R2 24 R10 37 A9 50 A3 12 R3 25 R11 38 B9 51 A2 13 P2 26 M10 39 A10 52 B2 Boundary Scan Exit Order (1M x 72) Bit # 209
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CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Current into Outputs (LOW) ........................................ 20 mA Maximum Ratings Static Discharge Voltage.......................................... > 2001V Exceeding maximum ratings may impair the useful life of the (MIL-STD-883, Method 3015) device. These user guidelines are not tested. Latch up Current.................................................... > 200 mA Storage Temperature ................................. –65°C to +150°C Operating Ran
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CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Electrical Characteristics [12, 13] Over the Operating Range (continued) Parameter Description Test Conditions Min Max Unit I Automatic CE Max. V , Device Deselected, 4.0-ns cycle, 250 MHz 200 mA SB3 DD Power Down V ≤ 0.3V or IN 5.0-ns cycle, 200 MHz 200 mA Current—CMOS Inputs V > V − 0.3V, IN DDQ f = f = 1/t 6.0-ns cycle, 167 MHz 200 mA MAX CYC I Automatic CE Max. V , Device Deselected, All speed grades 135 mA SB4 DD Power Down V ≥ V or V ≤ V , f = 0
