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CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
36-Mbit (1M x 36/2M x 18/512K x 72)
Pipelined SRAM with NoBL™ Architecture
Features Functional Description
• Pin-compatible and functionally equivalent to ZBT™ The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are
2.5V, 1M x 36/2M x 18/512 x 72 Synchronous pipelined burst
• Supports 250-MHz bus operations with zero wait states
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.
— Available speed grades are 250, 200 and 167 MHz
They are designed to support
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CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Logic Block Diagram–CY7C1462AV25 (2M x 18) ADDRESS A0, A1, A REGISTER 0 A1 A1' D1 Q1 A0 BURST A0' D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O U U T T P S D P U E U ADV/LD A T N T T WRITE REGISTRY S A MEMORY R E B AND DATA COHERENCY DQs BWa WRITE E ARRAY U S CONTROL LOGIC G DRIVERS A F T DQPa I M E F BWb S DQPb P E E T S R R E S I R N WE S G E E INPUT INPUT REGISTER 1 E REGISTER 0 E OE READ LOGIC CE1 CE2 CE3
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CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Pin Configurations 100-pin TQFP Pinout DQPc 1 NC 1 A DQPb 80 80 DQc 2 NC 2 DQb NC 79 79 DQc 3 DQb NC 3 NC 78 78 V 4 V DDQ 4 V DDQ 77 DDQ V 77 DDQ V 5 V V 5 SS SS V 76 SS SS 76 DQc 6 NC 6 DQb NC 75 75 DQc 7 DQb NC 7 DQP 74 74 DQc 8 DQb DQb 8 DQa 73 73 DQc 9 DQb DQb 9 DQa 72 72 V V SS 10 V SS SS 10 V 71 71 SS V V DDQ DDQ 11 V 11 V 70 DDQ 70 DDQ DQc 12 DQb DQb 12 DQa 69 69 DQc 13 DQb DQb 13 DQa 68 68 NC NC 14 V 14 V 67 SS CY7C1460AV25 67 SS V V DD 15 NC D
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CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Pin Configurations (continued) 165-ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1460AV25 (1M × 36) 1 2 3 4 567 89 10 11 A A A A NC/576M ADV/LD NC CE BW BW CE CEN 1 c b 3 NC/1G CE2 A NC B A BW BW CLK WE OE A d a C DQP NC V V V V V V V NC DQP c DDQ SS SS SS SS SS DDQ b D DQ DQ V V V V V V V DQ DQ c c DDQ DD SS SS SS DD DDQ b b DQ V V V V DQ DQ E DQ V V V c c DDQ DD SS SS SS DD DDQ b b F DQ DQ V V V V V V V DQ DQ c c DDQ DD SS SS SS DD DDQ b b G DQ DQ V V V V
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CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Pin Configurations (continued) 209-ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1464AV25 (512K x 72) 12 3456789 10 11 A DQg DQg A CE A DQb CEAA ADV/LD DQb 3 2 DQg B DQg A BWS DQb BWS BWS NC WE b BWS DQb c g f C DQg DQg NC/576M NC BWS CE BWS BWS DQb BWS DQb d 1 e a h D DQg DQg NC/1G NC NC V OE V NC DQb SS SS DQb E DQPg DQPc V V V V V V V DDQ DDQ DD DD DD DDQ DDQ DQPf DQPb DQc F DQc V V V NC V V DQf V SS SS SS SS SS DQf SS G DQc DQc V V V V V V DDQ DDQ NC DD DQ
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CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Pin Definitions (continued) Pin Name I/O Type Pin Description CE Input- Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with 1 Synchronous CE and CE to select/deselect the device. 2 3 CE Input- Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with 2 Synchronous CE and CE to select/deselect the device. 1 3 CE Input- Chip Enable 3 Input, active LOW. Sampled on the rising edge
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CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Functional Overview the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are cycle. Therefore, the type of access (Read or Write) is synchronous-pipelined Burst NoBL SRAMs designed specifi- maintained throughout the burst sequence. cally to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers
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CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 CY7C1460AV25, BW for CY7C1460AV25 and BW for a,b,c,d a,b Interleaved Burst Address Table CY7C1462AV25) inputs must be driven in each cycle of the (MODE = Floating or V ) DD burst write in order to write the correct bytes of data. First Second Third Fourth Sleep Mode Address Address Address Address The ZZ input pin is an asynchronous input. Asserting ZZ A1,A0 A1,A0 A1,A0 A1,A0 places the SRAM in a power conservation “sleep” mode. Two 00 01 10 11 clock cy
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CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 [1, 2, 3, 8] Partial Write Cycle Description Function (CY7C1460AV25) WE BW BW BW BW d c b a Read H X X X X Write – No bytes written L H H H H Write Byte a – (DQ and DQP) L HHH L a a Write Byte b – (DQ and DQP)LHHLH b b Write Bytes b, a L H H L L Write Byte c – (DQ and DQP)LHLHH c c Write Bytes c, a L H L H L Write Bytes c, b L H LL L H Write Bytes c, b, a L H L L L Write Byte d – (DQ and DQP)LLHHH d d Write Bytes d, a L L H H L Write Bytes d, b L LHLH
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CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Test Data-In (TDI) IEEE 1149.1 Serial Boundary Scan (JTAG) The TDI ball is used to serially input information into the The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 incor- registers and can be connected to the input of any of the porates a serial boundary scan test access port (TAP). This registers. The register between TDI and TDO is chosen by the part is fully compliant with 1149.1. The TAP operates using instruction that is loaded into the TAP instruction
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CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 When the TAP controller is in the Capture-IR state, the two SAMPLE Z least significant bits are loaded with a binary “01” pattern to The SAMPLE Z instruction causes the boundary scan register allow for fault isolation of the board-level serial test data path. to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts Bypass Register the output bus into a High-Z state until the next command is To
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CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 When this scan cell, called the “extest output bus tri-state,” is loaded into that shift-register cell will latch into the preload latched into the preload register during the “Update-DR” state register. When the EXTEST instruction is entered, this bit will in the TAP controller, it will directly control the state of the directly control the output Q-bus pins. Note that this bit is output (Q-bus) pins, when the EXTEST is entered as the preset HIGH to enab
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CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 2.5V TAP AC Test Conditions 1.8V TAP AC Test Conditions Input pulse levels ............................................... V to 2.5V Input pulse levels..................................... 0.2V to V – 0.2 SS DDQ Input rise and fall time .................................................... 1 ns Input rise and fall time .....................................................1 ns Input timing reference levels .........................................1.25V Inpu
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CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Scan Register Sizes Register Name Bit Size (x36) Bit Size (x18) Bit Size (x72) Instruction 3 3 3 Bypass 1 1 1 ID 32 32 32 Boundary Scan Order (165-ball FBGA package) 89 89 – Boundary Scan Order (209-ball FBGA package) – – 138 Identification Codes Instruction Code Description EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. IDCODE 001 Loads the ID register with the vendo
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CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 [12] 165-ball FBGA Boundary Scan Order CY7C1460AV25 (1M x 36), CY7C1462AV25 (2M x 18) Bit# Ball ID Bit# Ball ID Bit# Ball ID Bit# Ball ID 1N6 26 E11 51 A3 76 N1 2N7 27 D11 52 A2 77 N2 3 N10 28 G10 53B2 78P1 4P11 29 F10 54 C2 79 R1 5 P8 30 E10 55 B1 80 R2 6 R8 31 D10 56 A1 81 P3 7R9 32 C11 57 C1 82 R3 8P9 33 A11 58 D1 83 P2 9P10 34 B11 59E1 84 R4 10 R10 35 A10 60 F1 85 P4 11 R11 36 B10 61 G1 86 N5 12 H11 37 A9 62 D2 87 P6 13 N11 38 B9 63 E2 88 R6 14 M11 39
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CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 [12, 13] 209-ball FBGA Boundary Scan Order CY7C1464AV25 (512K x 72) Bit# Ball ID Bit# Ball ID Bit# Ball ID Bit# Ball ID 1 W6 36 F6 71 H6 106 K3 2 V6 37 K8 72 C6 107 K4 3 U6 38 K9 73 B6 108 K6 4 W7 39 K10 74 A6 109 K2 5V7 40 J11 75 A5 110 L2 6 U7 41 J10 76 B5 111 L1 7T7 42 H11 77 C5 112 M2 8 V8 43 H10 78 D5 113 M1 9 U8 44 G11 79 D4 114 N2 10 T8 45 G10 80 C4 115 N1 11 V9 46 F11 81 A4 116 P2 12 U9 47 F10 82 B4 117 P1 13 P6 48 E10 83 C3 118 R2 14 W11 49 E11 8
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CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Current into Outputs (LOW)......................................... 20 mA Maximum Ratings Static Discharge Voltage.......................................... > 2001V (Above which the useful life may be impaired. For user guide- (per MIL-STD-883, Method 3015) lines, not tested.) Latch-up Current.................................................... > 200 mA Storage Temperature .................................–65°C to +150°C Operating Range Ambient Temperatu
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CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 [16] Capacitance 100 TQFP 165 FBGA 209 FBGA Parameter Description Test Conditions Max. Max. Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 6.5 7 5 pF IN A V = 2.5V V = 2.5V DD DDQ C Clock Input Capacitance 3 7 5 pF CLK C Input/Output Capacitance 5.5 6 7 pF I/O [16] Thermal Resistance 100 TQFP 165 FBGA 209 FBGA Parameters Description Test Conditions Package Package Package Unit Θ Thermal Resistance Test conditions follow standard 25.21 20.8 25.31 °C/W
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CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 [21, 22] Switching Characteristics Over the Operating Range –250 –200 –167 Parameter Description Min. Max. Min. Max. Min. Max. Unit [17] t V (typical) to the first access read or write 1 1 1 ms Power CC Clock t Clock Cycle Time 4.0 5.0 6.0 ns CYC F Maximum Operating Frequency 250 200 167 MHz MAX t Clock HIGH 1.5 2.0 2.4 ns CH t Clock LOW 1.5 2.0 2.4 ns CL Output Times t Data Output Valid After CLK Rise 2.6 3.2 3.4 ns CO t OE LOW to Output Valid 2.6 3.0 3.
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CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 Switching Waveforms [23, 24, 25] Read/Write/Timing 123 456789 10 t CYC CLK t t t t CENS CENH CL CH CEN t t CES CEH CE ADV/LD WE BWx A1 A2 A3 A4 A5 A6 A7 ADDRESS t CO t t DS DH t t t t DOH CLZ OEV CHZ t t AS AH Data D(A1) D(A2) D(A2+1) Q(A3) Q(A4) Q(A4+1) D(A5) Q(A6) In-Out (DQ) t OEHZ t DOH t OELZ OE WRITE WRITE BURST READ READ BURST WRITE READ WRITE DESELECT D(A1) D(A2) WRITE Q(A3) Q(A4) READ D(A5) Q(A6) D(A7) D(A2+1) Q(A4+1) DON’T CARE UNDEFINED [23, 2
