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CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
72-Mbit DDR-II+ SRAM 2-Word Burst
Architecture (2.0 Cycle Read Latency)
Features Functional Description
■ 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36) The CY7C1546V18, CY7C1557V18, CY7C1548V18, and
CY7C1550V18 are 1.8V Synchronous Pipelined SRAM
■ 375 MHz clock for high bandwidth
equipped with DDR-II+ architecture. The DDR-II+ consists of an
SRAM core with advanced synchronous peripheral circuitry.
■ 2-word burst for reducing address bus fr
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4M x 8 Array 4M x 9 Array 4M x 8 Array 4M x 9 Array CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 Logic Block Diagram (CY7C1546V18) Write Write 22 A Reg (21:0) Reg Address Register LD 8 K Output CLK K Logic R/W Gen. Control DOFF Read Data Reg. 16 CQ V REF 8 8 Reg. CQ Reg. Control R/W 8 Logic DQ [7:0] 8 NWS [1:0] Reg. 8 QVLD Logic Block Diagram (CY7C1557V18) Write Write 22 A Reg (21:0) Reg Address Register LD 9 K Output CLK K Logic R/W Gen. Control DOFF Read Data Reg. 18 CQ V REF 9 9 Reg. CQ
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1M x 36 Array 2M x 18 Array 2M x 18 Array 1M x 36 Array CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 Logic Block Diagram (CY7C1548V18) Write Write 21 A Reg (20:0) Reg Address Register LD 18 K Output CLK K Logic R/W Gen. Control DOFF Read Data Reg. 36 CQ V REF 18 18 Reg. CQ Reg. Control R/W Logic DQ [17:0] BWS 18 18 [1:0] Reg. 18 QVLD Logic Block Diagram (CY7C1550V18) Write Write 20 A Reg (19:0) Reg Address Register LD 36 K Output CLK K Logic R/W Gen. Control DOFF Read Data Reg. 72 CQ V REF
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CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 Pin Configuration [2] The pin configuration for CY7C1546V18, CY7C1557V18, CY7C1548V18, and CY7C1550V18 follow. 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1546V18 (8M x 8) 1 2 3 4 5 6 7 8 9 10 11 A CQ AA R/W NWS K NC/144M LD AA CQ 1 B NC NC NC A NC/288M K NWS ANC NC DQ3 0 C NC NC NC V AAA V NC NC NC SS SS D NC NC NC V V V V V NC NC NC SS SS SS SS SS E NC NC DQ4 V V V V V NC NC DQ2 DDQ SS SS SS DDQ F NC NC NC V V V V V NC NC NC DDQ DD SS DD DDQ
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CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 Pin Configuration (continued) [2] The pin configuration for CY7C1546V18, CY7C1557V18, CY7C1548V18, and CY7C1550V18 follow. 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1548V18 (4M x 18) 1 2 3 4 5 6 7 8 9 10 11 A CQ AA R/W BWS K NC/144M LD AA CQ 1 B NC DQ9 NC A NC/288M K BWS ANC NC DQ8 0 C NC NC NC V ANC A V NC DQ7 NC SS SS D NC NC DQ10 V V V V V NC NC NC SS SS SS SS SS E NC NC DQ11 V V V V V NC NC DQ6 DDQ SS SS SS DDQ F NC DQ12 NC V V V V V NC
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CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 Pin Definitions Pin Name IO Pin Description Data Input or Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid DQ Input and [x:0] write operations. These pins drive out the requested data during a read operation. Valid data is driven Output Synchronous out on the rising edge of both the K and K clocks during read operations. When read access is deselected, Q are automatically tri-stated. [x:0] CY7C1546V18 − DQ
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CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 Pin Definitions (continued) Pin Name IO Pin Description ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q output impedance are set to 0.2 x RQ, where RQ is a resistor [x:0] connected between ZQ and ground. Alternatively, this pin is connected directly to V and enables DDQ the minimum impedance mode. This pin is not connected directly to GND or left unconnec
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CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 the positive input clock (K). Doing so pipelines the data flow such Functional Overview that 18 bits of data is transferred into the device on every rising edge of the input clocks (K and K). The CY7C1546V18, CY7C1557V18, CY7C1548V18, and CY7C1550V18 are synchronous pipelined Burst SRAMs When the write access is deselected, the device ignores all equipped with a DDR interface. inputs after the pending write operations are completed. Accesses ar
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CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 Echo Clocks DLL Echo clocks are provided on the DDR-II+ to simplify data capture These chips use a Delay Lock Loop (DLL) that is designed to on high-speed systems. Two echo clocks are generated by the function between 120 MHz and the specified maximum clock DDR-II+. CQ is referenced with respect to K and CQ is refer- frequency. The DLL may be disabled by applying ground to the enced with respect to K. These are free-running clocks and are DOFF pi
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CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 Truth Table [3, 4, 5, 6, 7, 8] The truth table for CY7C1546V18, CY7C1557V18, CY7C1548V18, and CY7C1550V18 follows. Operation K LD R/W DQ DQ Write Cycle: L-H L L D(A) at K(t + 1) ↑ D(A+1) at K(t + 1) ↑ Load address; wait one cycle; input write data on consecutive K and K rising edges. Read Cycle: (2.0 cycle Latency) L-H L H Q(A) at K(t + 2) ↑ Q(A+1) at K(t + 2) ↑ Load address; wait two cycle; read data on consecutive K and K rising edges. NOP:
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CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 Write Cycle Descriptions [3, 9] The write cycle description table for CY7C1557V18 follows. BWS K K Comments 0 L L–H – During the data portion of a write sequence, the single byte (D ) is written into the device. [8:0] L – L–H During the data portion of a write sequence, the single byte (D ) is written into the device. [8:0] H L–H – No data is written into the device during this portion of a write operation. H – L–H No data is written into the de
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CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 Instruction Register IEEE 1149.1 Serial Boundary Scan (JTAG) Three-bit instructions can be serially loaded into the instruction These SRAMs incorporate a serial boundary scan Test Access register. This register is loaded when it is placed between the TDI Port (TAP) in the FBGA package. This part is fully compliant with and TDO pins, as shown in TAP Controller Block Diagram on IEEE Standard #1149.1-2001. The TAP operates using JEDEC page 15. Upon
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CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 IDCODE The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required, that is, while the data The IDCODE instruction loads a vendor-specific, 32-bit code into captured is shifted out, the preloaded data can be shifted in. the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the BYPASS device when the TAP controller enters the Shift-DR state. The W
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CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 TAP Controller State Diagram [10] The state diagram for the TAP controller follows. TEST-LOGIC 1 RESET 0 1 1 1 SELECT TEST-LOGIC/ SELECT 0 IDLE DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 0 0 SHIFT-DR SHIFT-IR 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 0 0 PAUSE-DR PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-IR UPDATE-DR 1 1 0 0 Note 10. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-06550 Rev.
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CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 TAP Controller Block Diagram 0 Bypass Register 2 1 0 Selection Selection TDI TDO Instruction Register Circuitry Circuitry 31 30 29 . . 2 1 0 Identification Register . 108 . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics [11, 12, 13] Over the Operating Range Parameter Description Test Conditions Min Max Unit V Output HIGH Voltage I = −2.0 mA 1.4 V OH1 OH V Output HIGH Voltage I = −100 μA1.6 V OH2 OH V Ou
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CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 TAP AC Switching Characteristics [12, 14] Over the Operating Range Parameter Description Min Max Unit t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH 20 ns TH t TCK Clock LOW 20 ns TL Setup Times t TMS Setup to TCK Clock Rise 5 ns TMSS t TDI Setup to TCK Clock Rise 5 ns TDIS t Capture Setup to TCK Rise 5 ns CS Hold Times t TMS Hold after TCK Clock Rise 5 ns TMSH t TDI Hold after Clock Rise 5 ns TDIH t Capture
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CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 Identification Register Definitions Value Instruction Field Description CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18 Revision Number 000 000 000 000 Version number. (31:29) Cypress Device ID 11010111100000100 11010111100001100 11010111100010100 11010111100100100 Defines the type of (28:12) SRAM. Cypress JEDEC ID 00000110100 00000110100 00000110100 00000110100 Enables unique (11:1) identification of SRAM vendor. ID Register 1111 Indicates t
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CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 Boundary Scan Order Bit Number Bump ID Bit Number Bump ID Bit Number Bump ID Bit Number Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P29 9G 57 5B85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N32 9F 60 5C88 2K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C
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CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 DLL Constraints Power Up Sequence in DDR-II+ SRAM ■ DLL uses K clock as its synchronizing input. The input must DDR-II+ SRAMs must be powered up and initialized in a have low phase jitter, which is specified as t . KC Var predefined manner to prevent undefined operations. During power up, when the DOFF is tied HIGH, the DLL is locked after ■ The DLL functions at frequencies down to 120 MHz. 2048 cycles of stable clock. ■ If the input clock is un
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CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18 Current into Outputs (LOW) ........................................ 20 mA Maximum Ratings Static Discharge Voltage (MIL-STD-883, M. 3015)... >2001V Exceeding maximum ratings may impair the useful life of the Latch up Current..................................................... >200 mA device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Power A
