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CY7C68300C/CY7C68301C
CY7C68320C/CY7C68321C
EZ-USB AT2LP™ USB 2.0 to ATA/ATAPI Bridge
• Supports CompactFlash and one ATA/ATAPI device
Features
• Supports board-level manufacturing test using the USB I/F
• Fixed-function mass storage device—requires no firmware
• Can place the ATA interface in high impedance (Hi-Z) to
• Two power modes: Self-powered and USB bus-powered to
allow sharing of the ATA bus with another controller (i.e., an
enable bus powered CF readers and truly portable USB
IEEE-
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CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C data transfer rates by minimizing losses due to device seek Applications times. The ATA interface supports ATA PIO modes 0, 3, and 4, The CY7C68300C/301C and CY7C68320C/321A implement multiword DMA mode 2, and Ultra DMA modes 2, 3, and 4. a USB 2.0 bridge for all ATA/ATAPI-6 compliant mass storage The device initialization process is configurable, enabling the devices, such as the following: AT2LP to initialize ATA/ATAPI devices without software inter-
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CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Pin Diagrams The AT2LP is available in different package types to meet a variety of design needs. The CY7C68320C/321C is available in 56-pin QFN and 100-pin TQFP packages to provide the greatest flexibility for new designs. The CY7C68300C/301C is available in 56-pin SSOP and QFN package types to ensure backward compatibility with CY7C68300A designs. Figure 2. 56-pin SSOP Pinout (CY7C68300C/CY7C68301C only) 1 56 DD13 DD12 2 55 DD14 DD11 3 54 DD15 DD10
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CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Figure 3. 56-pin QFN Pinout (CY7C68300C/CY7C68301C) IORDY 1 42 RESET# DMARQ 2 41 GND AVCC 3 40 ARESET# XTALOUT 4 39 DA2 (VBUS_PWR_VALID) XTALIN 5 38 CS1# EZ-USB AT2LP AGND 6 37 CS0# CY7C68300C VCC 7 36 DRVPWRVLD (DA2) DPLUS 8 35 DA1 CY7C68301C DMINUS 9 34 DA0 GND 10 56-pin QFN 33 INTRQ VCC 11 32 VCC GND 12 31 DMACK# NOTE: Italic labels denote pin functionality (PU10K) PWR500# 13 during CY7C68300A compatibility mode. 30 DIOR# GND 14 29 DIOW# Document
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CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Figure 4. 56-pin SSOP Pinout (CY7C68320C/CY7C68321C) 1 56 DD13 DD12 2 DD14 DD11 55 3 54 DD15 DD10 4 GND DD9 53 5 GPIO2 DD8 52 6 51 VCC VBUS_ATA_ENABLE 7 GND VCC 50 8 49 IORDY RESET# 9 DMARQ GND 48 10 AVCC ARESET# 47 11 46 XTALOUT DA2 12 XTALIN CS1# 45 13 44 AGND CS0# 14 VCC GPIO0 43 15 DPLUS DA1 42 EZ-USB AT2LP 16 41 DMINUS DA0 CY7C68320C 17 GND INTRQ 40 CY7C68321C 18 39 VCC VCC 19 GND 56-pin SSOP DMACK# 38 20 GPIO1 DIOR# 37 21 36 GND DIOW# 22 SCL GND
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CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Figure 5. 56-pin QFN Pinout (CY7C68320C/CY7C68321C) IORDY 1 42 RESET# DMARQ 2 41 GND AVCC 3 40 ARESET# XTALOUT 4 39 DA2 XTALIN 5 38 CS1# EZ-USB AT2LP AGND 6 37 CS0# CY7C68320C VCC 7 36 GPIO0 DPLUS 8 35 DA1 CY7C68321C DMINUS 9 34 DA0 GND 10 33 INTRQ 56-pin QFN VCC 11 32 VCC GND 12 31 DMACK# GPIO1 13 30 DIOR# GND 14 29 DIOW# Document 001-05809 Rev. *A Page 6 of 42 [+] Feedback SCL 15 56 GND SDA 16 55 VCC VCC 17 54 GPIO2 DD0 18 53 GND DD1 19 52
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CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Figure 6. 100-pin TQFP Pinout (CY7C68320C/CY7C68321C only) 1 80 VCC DD8 2 GND VBUS_ATA_ENABLE 79 3 78 IORDY VCC 4 DMARQ RESET# 77 5 76 GND NC 6 GND GND 75 7 74 GND ARESET# 8 GND DA2 73 9 72 AVCC CS1# 10 XTALOUT CS0# 71 11 70 XTALIN DRVPWRVLD 12 AGND DA1 69 13 68 NC DA0 EZ-USB AT2LP 14 NC INTRQ 67 15 66 NC CY7C68320A C VCC 16 VCC GND 65 CY7C68321A C 17 64 DPLUS NC 18 DMINUS NC 63 100-pin TQFP 19 62 GND VBUSPWRD 20 VCC NC 61 21 60 GND NC 22 SYSIRQ NC 59
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CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Pin Descriptions 68300C/01C and 68320C/321C pinouts for the 56-pin packages. For information on the CY7C68300A pinout, refer The following table lists the pinouts for the 56-pin SSOP, 56-pin to the CY7C68300A data sheet that is found in the ’EZ-USB QFN and 100-pin TQFP package options for the AT2LP. Refer AT2’ folder of the CY4615C reference design kit CD. to the “Pin Diagrams” on page 3 for differences between the Table 1. AT2LP Pin Descriptions Note
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CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Table 1. AT2LP Pin Descriptions Note: (Italic pin names denote pin functionality during CY7C68300A compatibility mode) (continued) 100 56 56 Pin Default State Pin Name Pin Description TQFP QFN SSOP Type at Startup 2 30 16 23 SDA IO Data signal for I C interface. (See “SCL, SDA” on page 11). Apply a 2.2k pull up resistor. 31 N/A N/A NC No connect. 32 33 17 24 V PWR V . Connect to 3.3V power source. CC CC [1] 34 18 25 DD0 IO Hi-Z ATA data bit 0. [1] 3
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CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Table 1. AT2LP Pin Descriptions Note: (Italic pin names denote pin functionality during CY7C68300A compatibility mode) (continued) 100 56 56 Pin Default State Pin Name Pin Description TQFP QFN SSOP Type at Startup [1] 68 34 41 DA0 O/Z Driven HIGH ATA address. after 2 ms delay [1] 69 35 42 DA1 O/Z Driven HIGH ATA address. after 2 ms delay [3] [3] 70 36 43 DRVPWRVLD I Input Device presence detect. (See “DRVPWRVLD” on (DA2) page 13). Configurable log
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CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Table 1. AT2LP Pin Descriptions Note: (Italic pin names denote pin functionality during CY7C68300A compatibility mode) (continued) 100 56 56 Pin Default State Pin Name Pin Description TQFP QFN SSOP Type at Startup [3] [3] 100 54 5 ATAPUEN IO Bus-powered ATA pull up voltage source (see (NC) “ATAPUEN” on page 14). Alternate function: General purpose input when the EEPROM configuration byte 8 has bit 7 set to ‘1’. The input value is reported through
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CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C SYSIRQ inputs or outputs, with byte 0x09 of the configuration data. The state of any GPIO pin that is not set as an input is reported as The SYSIRQ pin provides a way for systems to request service ‘0’ in the EP1 data. from host software by using the USB Interrupt pipe on endpoint 1 (EP1). If the AT2LP has no pending interrupt data to return, Table 3 gives the bitmap for the data returned on the interrupt USB interrupt pipe data requests are NAKed. If
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CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Figure 8. SYSIRQ Latching Algorithm No No USB Interrupt SYSIRQ=1? Pipe Polled? Yes Yes Latch State of IO Pins Yes Set Int_Data = 1 Int_Data = 1? No No NAK Request Yes Int_Data = 0 and SYSIRQ=0? Return Interrupt Data Set Int_Data = 0 DRVPWRVLD • The host can modify the settings of the GPIO pins during operation. This is done with vendor-specific commands When this pin is enabled with bit 0 of configuration address described in “Programming the EEPR
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CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C interface and the attached mass storage device, especially if PWR500# Ultra DMA Mode is used. The AT2LP asserts PWR500# to indicate that VBUS current may be drawn up to the limit specified by the bMaxPower field VBUS_ATA_ENABLE of the USB configuration descriptors. If the AT2LP enters a VBUS_ATA_ENABLE is typically used to indicate to the low-power state, PWR500# is deasserted. When normal AT2LP that power is present on VBUS. This pin is polled by oper
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CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C HID Functions for Button Controls Cypress’s CY7C68320C/CY7C68321C has the capability of CY4615C files, provides an easy way to enable and modify the supporting Human Interface Device (HID) signaling to the HID features of the AT2LP. host. GPIO pins can be individually set as inputs or outputs, with If there is a HID descriptor in the configuration data, the GPIO byte 0x09 of the configuration data, allowing for a mix of HID pins that are set as input
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CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Table 6. ATACB Field Descriptions Byte Field Name Field Description 0 bVSCBSignature This field indicates to the CY7C68300C/CY7C68301C that the ATACB contains a vendor-specific command block. This value of this field must match the value in EEPROM address 0x04 for the command to be recognized as a vendor-specific ATACB command. 1 bVSCBSubCommand This field must be set to 0x24 for ATACB commands. 2 bmATACBActionSelect This field controls the execut
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CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Table 6. ATACB Field Descriptions (continued) Byte Field Name Field Description 3 bmATACBRegisterSelect This field controls which of the taskfile register read or write accesses occur. Taskfile read data is always 8 bytes in length, and unselected register data are returned as 0x00. Register accesses occur in sequential order as outlined below (0 to 7): Bit 0 (0x3F6) Device Control/Alternate Status Bit 1 (0x1F1) Features/Error Bit 2 (0x1F2) Sector C
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CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Operating Modes The different modes of operation and EEPROM information is not a valid mode of operation if no factory programming are presented in the following sections. has been done. • If an EEPROM signature of 0x4D4D is found, the Operational Mode Selection Flow CY7C68300C/CY7C68301C uses the same pinout and 2 During the power-up sequence, the AT2LP queries the I C bus EEPROM format as the CY7C68300A (EZ-USB AT2+). for an EEPROM. The AT2LP the
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CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Fused Memory Data ATAPI command for EEPROM accesses (CfgCB) and one for board level testing (MfgCB), as described in the following When no EEPROM is detected at startup, the AT2LP sections. enumerates with the VID/PID/DID values that are stored in the fused memory space. These values can be programmed into There is a convenient method available for starting the AT2LP the AT2LP during chip manufacturing for high volume applica- in Board Manufacturing Te
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CY7C68300C/CY7C68301C CY7C68320C/CY7C68321C Table 8. Example CfgCB Offset CfgCB Byte Descriptions Bits 765432 10 0 bVSCBSignature (set in configuration bytes) 001001 00 1 bVSCBSubCommand (must be 0x26) 001001 10 2 Reserved (must be set to zero) 000000 00 3 Data Source (must be set to 0x02) 000000 10 4 Start Address (LSB) (must be set to zero) 000000 00 5 Start Address (MSB) (must be set to zero) 000000 00 6–15 Reserved (must be set to zero) 000000 00 MfgCB Mfg_read The mfg_load and mfg_read ven
