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CY7C63413C
CY7C63513C
CY7C63613C
Low-Speed High I/O, 1.5-Mbps USB Controller
• Operating voltage from 4.0V to 5.5V DC
Features
• Operating temperature from 0 to 70 degrees Celsius
• Low-cost solution for low-speed applications with high
• CY7C63413C available in 40-pin PDIP, 48-pin SSOP, 48-
I/O requirements such as keyboards, keyboards with
pin SSOP - Tape reel, all in Lead-Free versions for
integrated pointing device, gamepads, and many
production
others
• CY7C63513C available in 48-pin
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CY7C63413C CY7C63513C CY7C63613C The sink current for each DAC I/O pin can be individually GPIO ports. The timer bits cause an interrupt (if enabled) when programmed to one of sixteen values using dedicated Isink the bit toggles from LOW “0” to HIGH “1.” The USB endpoints registers. DAC bits [1:0] can be used as high current outputs interrupt after either the USB host or the USB controller sends with a programmable sink current range of 3.2 to 16 mA a packet to the USB. The DAC ports have an ad
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CY7C63413C CY7C63513C CY7C63613C . Pin Configuration Logic Block Diagram CY7C63513C CY7C63413C 6-MHz ceramic resonator 48-pin SSOP 48-pin SSOP D+ 1 48 V D+ 1 48 V CC CC 2 47 Vss 2 47 Vss D– D– OSC 3 46 P3[6] 3 46 P3[6] P3[7] P3[7] 4 P3[4] P3[5] 4 P3[4] P3[5] 45 45 P3[2] P3[2] P3[3] 5 44 12 MHz 6 MHz P3[3] 5 44 P3[0] 43 P3[0] P3[1] 6 43 P3[1] 6 P2[6] P2[6] P2[7] 7 42 P2[7] 7 42 P2[4] P2[4] P2[5] 8 41 P2[5] 8 41 P2[3] 9 40 P2[2] P2[3] 9 40 P2[2] 12-MHz USB USB D+ P2[1] 10 39 P2[0] P2[1] 10 39 P2[
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CY7C63413C CY7C63513C CY7C63613C Pin Definitions CY7C63413C CY7C63513C CY7C63613C Name I/O 40-Pin 48-Pin Die 48-Pin 24-Pin Description D+, D– I/O 1,2 1,2 1,2 1,2 1,2 USB differential data; PS/2 clock and data signals P0[7:0] I/O 15,26,16 17,32,18 17,32,18, 17,32,18,31, 7, 18, 8, 17, 9, GPIO port 0 capable of sinking 7 mA 25,17,24 31,19,30 31,19,30, 19,30,20,29 16, 10, 15 (typical) 18,23 20,29 20,29 P1[3:0] I/O 11,30,12, 11,38,12, 11,38,12, 11,38,12,37, 5, 20, 6, 19 GPIO Port 1 capable of sink
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CY7C63413C CY7C63513C CY7C63613C During an interrupt acknowledge, interrupts are disabled and Data the 14-bit program counter, carry flag, and zero flag are written The “Data” address mode refers to a data operand that is as two bytes of data memory. The first byte is stored in the actually a constant encoded in the instruction. As an example, memory addressed by the program stack pointer, then the consider the instruction that loads A with the constant 0xE8: PSP is incremented. The second byte
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CY7C63413C CY7C63513C CY7C63613C Instruction Set Summary MNEMONIC operand opcode cycles MNEMONIC operand opcode cycles HALT 00 7 NOP 20 4 ADD A,expr data 01 4 INC A acc 21 4 ADD A,[expr] direct 02 6 INC X x 22 4 ADD A,[X+expr] index 03 7 INC [expr] direct 23 7 ADC A,expr data 04 4 INC [X+expr] index 24 8 ADC A,[expr] direct 05 6 DEC A acc 25 4 ADC A,[X+expr] index 06 7 DEC X x 26 4 SUB A,expr data 07 4 DEC [expr] direct 27 7 SUB A,[expr] direct 08 6 DEC [X+expr] index 28 8 SUB A,[X+expr] index
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CY7C63413C CY7C63513C CY7C63613C Memory Organization Program Memory Organization after reset Address 14-bit PC 0x0000 Program execution begins here after a reset 0x0002 USB Bus Reset interrupt vector 0x0004 128-µs timer interrupt vector 0x0006 1.024-ms timer interrupt vector 0x0008 USB address A endpoint 0 interrupt vector 0x000A USB address A endpoint 1 interrupt vector 0x000C USB address A endpoint 2 interrupt vector 0x000E Reserved 0x0010 Reserved 0x0012 Reserved 0x0014 DAC interrupt vector
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CY7C63413C CY7C63513C CY7C63613C Data Memory Organization into four areas: program stack, data stack, user variables and USB endpoint FIFOs as shown below: The CY7C63413C/513C/613C microcontrollers provide 256 bytes of data RAM. In normal usage, the SRAM is partitioned after reset Address 8-bit PSP 0x00 Program Stack begins here and grows upward 8-bit DSP user Data Stack begins here and grows downward The user determines the amount of memory required User Variables 0xE8 USB FIFO for Address A e
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CY7C63413C CY7C63513C CY7C63613C I/O Register Summary lator to the selected port. Indexed I/O Write (IOWX) adds the contents of X to the address in the instruction to form the port I/O registers are accessed via the I/O Read (IORD) and I/O address and writes data from the accumulator to the specified Write (IOWR, IOWX) instructions. IORD reads the selected port. Note that specifying address 0 (e.g., IOWX 0h) means port into the accumulator. IOWR writes data from the accumu- the I/O port is sele
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CY7C63413C CY7C63513C CY7C63613C Clock Distribution XTALOUT clk1x (to USB SIE) Clock clk2x Doubler (to Microcontroller) XTALIN 30 pF 30 pF Figure 2. Clock Oscillator On-chip Circuit processing does NOT push the program counter, carry flag, Clocking and zero flag onto program stack. That means the reset The XTAL and XTAL are the clock pins to the microcon- handler in firmware should initialize the hardware and begin IN OUT troller. The user can connect a low-cost ceramic resonator or executing t
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CY7C63413C CY7C63513C CY7C63613C initialization noted under “Reset,” bit 6 of the Processor Status General Purpose I/O Ports and Control Register is set to “1” to indicate to the firmware that a Watch Dog Reset occurred. Ports 0 to 2 provide 24 GPIO pins that can be read or written. Each port (8 bits) can be configured as inputs with internal pull- The Watch Dog Timer is a 2-bit timer clocked by a 4.096-ms ups, open drain outputs, or traditional CMOS outputs. Please clock (bit 11) from the free
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CY7C63413C CY7C63513C CY7C63613C Table 5. Port 3 Data Addr: 0x03 Port 3 Data P3[7] P3[6] P3[5] P3[4] P3[3] P3[2] P3[1] P3[0] R/W R/W R/W R/W R/W R/W R/W R/W Table 6. DAC Port Data Addr: 0x30 DAC Port Data Low current outputs High current outputs 0.2 mA to 1.0 mA typical 3.2 mA to 16 mA typical DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0] R/W R/W R/W R/W R/W R/W R/W R/W Port 3 has eight GPIO pins. Port 3 (8 bits) can be configured During reset, all of the bits in the GPIO to a def
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CY7C63413C CY7C63513C CY7C63613C Table 11.Possible Port Configurations Port Configuration bits Pin Interrupt Bit Driver Mode Interrupt Polarity 11 X Resistive - 10 0 CMOS Output disabled 10 1 Open Drain disabled 01 X Open Drain - 00 X Open Drain + (default) In “Resistive” mode, a 7-kΩ pull-up resistor is conditionally direction. If a port’s associated Interrupt Mask bits are cleared, enabled for all pins of a GPIO port. The resistor is enabled for those port bits are strictly outputs. If the In
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CY7C63413C CY7C63513C CY7C63613C Table 13.DAC Port Data Addr: 0x30 DAC Port Data Low current outputs High current outputs 0.2 mA to 1.0 mA typical 3.2 mA to 16 mA typical DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0] R/W R/W R/W R/W R/W R/W R/W R/W The DAC port provides the CY7C63513C with 8 program- this feature with an interrupt mask bit for each DAC I/O pin. mable current sink I/O pins. Writing a “1” to a DAC I/O pin Writing a “1” to a bit in this register enables interrupts from
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CY7C63413C CY7C63513C CY7C63613C 7. The USB Controller decodes the request and retrieves the USB Serial Interface Engine (SIE) Device descriptor from the program memory. The SIE allows the microcontroller to communicate with the 8. The host performs a control read sequence and the USB USB host. The SIE simplifies the interface between the micro- Controller responds by sending its Device descriptor over controller and USB by incorporating hardware that handles the the USB bus. following USB b
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CY7C63413C CY7C63513C CY7C63613C The Bus Activity bit is a “sticky” bit that indicates if any non-idle are cleared during a reset, setting the USB device address to USB event has occurred on the USB bus. The user firmware zero and marking this address as disabled. Figure 18 shows should check and clear this bit periodically to detect any loss the format of the USB Address Register. of bus activity. Writing a “0” to the Bus Activity bit clears it while Bit 7 (Device Address Enable) in the USB De
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CY7C63413C CY7C63513C CY7C63613C The ‘Acknowledge’ bit is set whenever the SIE engages in a While the ‘set-up’ bit is set, the CPU cannot write to the DMA transaction that completes with an ‘ACK’ packet. buffers at memory locations 0xE0 through 0xE7 and 0xF8 through 0xFF. This prevents an incoming set-up transaction The ‘set-up’ PID status (bit[7]) is forced HIGH from the start of from conflicting with a previous In data buffer filling operation the data packet phase of the set-up transaction,
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CY7C63413C CY7C63513C CY7C63613C upper 4 bits into a temporary register. When the firmware 12-bit Free-running Timer reads the upper 4 bits of the timer, it is actually reading the The 12-bit timer provides two interrupts (128 µs and 1.024 ms) count stored in the temporary register. The effect of this logic and allows the firmware to directly time events that are up to is to ensure a stable 12-bit timer value can be read, even when 4 ms in duration. The lower 8 bits of the timer can be read the
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CY7C63413C CY7C63513C CY7C63613C The “Single Step” (bit 1) is provided to support a hardware During Power-on Reset, the Processor Status and Control debugger. When single step is set, the processor will execute Register is set to 00010001, which indicates a Power-on Reset one instruction and halt (clear the run bit). This bit must be (bit 4 set) has occurred and no interrupts are pending (bit 7 cleared for normal operation. clear) yet. The “Interrupt Mask” (bit 2) shows whether interrupts are D
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CY7C63413C CY7C63513C CY7C63613C Interrupt Vectors 0x0000—which corresponds to the first entry in the Interrupt Vector Table. Because the JMP instruction is 2 bytes long, the The Interrupt Vectors supported by the USB Controller are interrupt vectors occupy 2 bytes. listed in Table 27. Although Reset is not an interrupt, per se, the first instruction executed after a reset is at PROM address Table 27.Interrupt Vector Assignments Interrupt Vector Number ROM Address Function not applicable 0x0000
