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CY7C1422BV18, CY7C1429BV18
CY7C1423BV18, CY7C1424BV18
36-Mbit DDR-II SIO SRAM 2-Word
Burst Architecture
Features Functional Description
■ 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) The CY7C1422BV18, CY7C1429BV18, CY7C1423BV18, and
CY7C1424BV18 are 1.8V Synchronous Pipelined SRAMs,
■ 300 MHz clock for high bandwidth
equipped with Double Data Rate Separate IO (DDR-II SIO)
■ 2-word burst for reducing address bus frequency
architecture. The DDR-II SIO consists of two separate ports: the
rea
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2M x 8 Array 2M x 9 Array 2M x 8 Array 2M x 9 Array CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Logic Block Diagram (CY7C1422BV18) 8 D [7:0] Write Write Data Reg Data Reg 21 Address A (20:0) Register LD K Control R/W CLK Logic K Gen. C DOFF Read Data Reg. C CQ 16 R/W 8 CQ Reg. Reg. V 8 REF Control 8 Logic LD 8 Reg. Q 8 [7:0] NWS [1:0] Logic Block Diagram (CY7C1429BV18) 9 D [8:0] Write Write Data Reg Data Reg 21 Address A (20:0) Register LD K Control R/W CLK Logic K Gen. C DOFF Read Dat
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1M x 18 Array 512K x 36 Array 1M x 18 Array 512K x 36 Array CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Logic Block Diagram (CY7C1423BV18) 18 D [17:0] Write Write Data Reg Data Reg 20 Address A (19:0) Register LD K Control R/W CLK Logic K Gen. C DOFF Read Data Reg. C CQ 36 R/W 18 CQ Reg. Reg. V 18 REF Control Logic 18 LD Reg. 18 Q 18 [17:0] BWS [1:0] Logic Block Diagram (CY7C1424BV18) 36 D [35:0] Write Write Data Reg Data Reg 19 Address A (18:0) Register LD K Control R/W CLK Logic K Ge
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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Pin Configuration [1] The pin configuration for CY7C1422BV18, CY7C1429BV18, CY7C1423BV18, and CY7C1424BV18 follow. 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1422BV18 (4M x 8) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/72M A R/W NWS K NC/144M LD AA CQ 1 B NC NC NC A NC/288M K NWS ANC NC Q3 0 C NC NC NC V AAA V NC NC D3 SS SS D NC D4 NC V V V V V NC NC NC SS SS SS SS SS E NC NC Q4 V V V V V NC D2 Q2 DDQ SS SS SS DDQ F NC NC NC V V V V V NC NC NC DDQ D
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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Pin Configuration (continued) [1] The pin configuration for CY7C1422BV18, CY7C1429BV18, CY7C1423BV18, and CY7C1424BV18 follow. 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1423BV18 (2M x 18) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/144M A R/W BWS K NC/288M LD A NC/72M CQ 1 B NC Q9 D9 A NC K BWS ANC NC Q8 0 C NC NC D10 V AAA V NC Q7 D8 SS SS D NC D11 Q10 V V V V V NC NC D7 SS SS SS SS SS E NC NC Q11 V V V V V NC D6 Q6 DDQ SS SS SS DDQ F NC Q12 D12 V V
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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Pin Definitions Pin Name IO Pin Description D Input- Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations. [x:0] CY7C1422BV18 - D Synchronous [7:0] CY7C1429BV18 - D [8:0] CY7C1423BV18 - D [17:0] CY7C1424BV18 - D [35:0] LD Input- Synchronous Load. This input is brought LOW when a bus cycle sequence is defined. This definition Synchronous includes address and read/write direction. All transactions op
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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Pin Definitions (continued) Pin Name IO Pin Description CQ Echo Clock CQ Referenced with Respect to C. This is a free-running clock and is synchronized to the input clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks is shown in the Switching Characteristics on page 23. CQ Echo Clock CQ Referenced with Respect to C. This is a free-running clock and is synchro
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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 are then written into the memory array at the specified location. Functional Overview Write accesses can be initiated on every rising edge of the positive input clock (K). This pipelines the data flow such that 18 The CY7C1422BV18, CY7C1429BV18, CY7C1423BV18, and bits of data can be transferred into the device on every rising CY7C1424BV18 are synchronous pipelined Burst SRAMs edge of the input clocks (K and K). equipped with a DDR-II Seperat
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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Echo Clocks DLL Echo clocks are provided on the DDR-II to simplify data capture These chips use a Delay Lock Loop (DLL) that is designed to on high-speed systems. Two echo clocks are generated by the function between 120 MHz and the specified maximum clock DDR-II. CQ is referenced with respect to C and CQ is referenced frequency. During power up, when the DOFF is tied HIGH, the with respect to C. These are free-running clocks and are DLL is l
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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Truth Table [2, 3, 4, 5, 6, 7] The truth table for CY7C1422BV18, CY7C1429BV18, CY7C1423BV18, and CY7C1424BV18 follows. Operation K LD R/W DQ DQ L-H L L D(A + 0) at K(t + 1)↑ D(A + 1) at K(t + 1)↑ Write Cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges. Read Cycle: L-H L H Q(A + 0) at C(t + 1)↑ Q(A + 1) at C(t + 2)↑ Load address; wait one and a half cycle; read data on consecutive C and C rising edges
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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Write Cycle Descriptions [2, 8] The write cycle description table for CY7C1429BV18 follows. BWS K K Comments 0 L L–H – During the Data portion of a write sequence, the single byte (D ) is written into the device. [8:0] ) is written into the device. L – L–H During the Data portion of a write sequence, the single byte (D [8:0] H L–H – No data is written into the device during this portion of a write operation. H – L–H No data is written into t
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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Instruction Register IEEE 1149.1 Serial Boundary Scan (JTAG) Three-bit instructions can be serially loaded into the instruction These SRAMs incorporate a serial boundary scan Test Access register. This register is loaded when it is placed between the TDI Port (TAP) in the FBGA package. This part is fully compliant with and TDO pins, as shown in TAP Controller Block Diagram on IEEE Standard #1149.1-2001. The TAP operates using JEDEC page 15. U
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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 IDCODE BYPASS The IDCODE instruction loads a vendor-specific, 32-bit code into When the BYPASS instruction is loaded in the instruction register the instruction register. It also places the instruction register and the TAP is placed in a Shift-DR state, the bypass register is between the TDI and TDO pins and shifts the IDCODE out of the placed between the TDI and TDO pins. The advantage of the device when the TAP controller enters the Shift-D
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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 TAP Controller State Diagram [9] The state diagram for the TAP controller follows. TEST-LOGIC 1 RESET 0 1 1 1 TEST-LOGIC/ SELECT SELECT 0 IDLE DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 0 0 SHIFT-DR SHIFT-IR 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 0 0 PAUSE-DR PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-IR UPDATE-DR 1 1 0 0 Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 001-07035 Rev. *D
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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 TAP Controller Block Diagram 0 Bypass Register 2 1 0 Selection Selection TDI TDO Instruction Register Circuitry Circuitry 31 30 29 . . 2 1 0 Identification Register . 108 . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics [10, 11, 12] Over the Operating Range Parameter Description Test Conditions Min Max Unit V Output HIGH Voltage I = −2.0 mA 1.4 V OH1 OH Output HIGH Voltage I = −100 μA1.6 V V OH2 OH
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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 TAP AC Switching Characteristics [13, 14] Over the Operating Range Parameter Description Min Max Unit t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH 20 ns TH t TCK Clock LOW 20 ns TL Setup Times t TMS Setup to TCK Clock Rise 5 ns TMSS t TDI Setup to TCK Clock Rise 5 ns TDIS t Capture Setup to TCK Rise 5 ns CS Hold Times t TMS Hold after TCK Clock Rise 5 ns TMSH t TDI Hold after Clock Rise 5 ns TDIH t Capt
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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Identification Register Definitions Value Instruction Field Description CY7C1422BV18 CY7C1429BV18 CY7C1423BV18 CY7C1424BV18 Revision Number 000 000 000 000 Version number. (31:29) Cypress Device ID 11010100010000111 11010100010001111 11010100010010111 11010100010100111 Defines the type of (28:12) SRAM. Cypress JEDEC ID 00000110100 00000110100 00000110100 00000110100 Allows unique (11:1) identification of SRAM vendor. ID Register 1111 Indi
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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P29 9G 57 5B85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N32 9F 60 5C88 2K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M 43
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~ ~ CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 DLL Constraints Power Up Sequence in DDR-II SRAM ■ DLL uses K clock as its synchronizing input. The input must DDR-II SRAMs must be powered up and initialized in a have low phase jitter, which is specified as t . KC Var predefined manner to prevent undefined operations. ■ The DLL functions at frequencies down to 120 MHz. Power Up Sequence ■ If the input clock is unstable and the DLL is enabled, then the ■ Apply power and drive DOFF eith
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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Current into Outputs (LOW) ........................................ 20 mA Maximum Ratings Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V Exceeding maximum ratings may impair the useful life of the Latch-up Current ................................................... > 200 mA device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Pow
