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CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
[1]
Features Functional Description
• Supports bus operation up to 250 MHz The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F
SRAM integrates 512K x 36/1M x 18 SRAM cells with
• Available speed grades are 250, 200, and 167 MHz
advanced synchronous peripheral circuitry and a two-bit
• Registered inputs and outputs for pipelined operation
counter for internal burst operation. All synchronous inputs are
• O
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F [3] Logic Block Diagram – CY7C1386D/CY7C1386F (512K x 36) ADDRESS A0,A1,A REGISTER 2 A[1:0] MODE ADV Q1 BURST CLK COUNTER AND LOGIC CLR Q0 ADSC ADSP DQ D,DQP D DQ D,DQP D BYTE BW D BYTE WRITE REGISTER WRITE DRIVER DQ c,DQP C DQ c,DQP C MEMORY BYTE BW C BYTE ARRAY OUTPUT WRITE DRIVER OUTPUT WRITE REGISTER SENSE DQs BUFFERS REGISTERS AMPS DQP A DQ B,DQP B E DQ B,DQP B DQP B BYTE BYTE BW B DQP C WRITE DRIVER WRITE REGISTER DQP D DQ A,DQP A DQ A,DQP A BYTE
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Pin Configurations 100-pin TQFP Pinout (3 Chip Enables) DQP C 1 80 DQP B NC A 1 80 DQ C 2 79 DQ B NC NC 2 79 DQ C 3 78 DQ B NC NC 3 78 V DDQ V 4 77 V DDQ DDQ 4 77 V DDQ V SSQ V 5 76 V SSQ SSQ 5 76 V SSQ DQ C DQ 6 75 NC B 6 75 NC DQ C DQ 7 74 NC B 7 74 DQP A DQ DQ C 8 73 B DQ B 8 73 DQ A DQ C 9 72 DQ B DQ B DQ 9 72 A V SSQ 10 71 V SSQ V SSQ V 10 71 SSQ V DDQ 11 70 V DDQ V DDQ V 11 70 DDQ DQ C 12 69 DQ B DQ B DQ 12 69 A DQ C 13 68 DQ DQ B DQ B 13 68 A NC
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Pin Configurations (continued) 119-Ball BGA Pinout (1 Chip Enable) CY7C1386F (512K x 36) 1 23 4 5 6 7 A V AA A A V DDQ ADSP DDQ B NC/288M A A ADSC A A NC/576M NC/144M A A V A A NC/1G C DD D DQ DQP V NC V DQP DQ C C SS SS B B DQ DQ V CE V DQ DQ E C C SS 1 SS B B V DQ V V DQ V F OE DDQ C SS SS B DDQ G DQ DQ BW BW DQ DQ ADV C C C B B B H DQ DQ V V DQ DQ C C SS GW SS B B J V V NC V NC V V DDQ DD DD DD DDQ K DQ DQ V CLK V DQ DQ D D SS SS A A L DQ DQ NC DQ DQ
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip Enable) CY7C1386D (512K x 36) 1 23 4 5 6 7 89 10 11 NC/288M A NC A A CE BW BW CE ADSC BWE ADV 1 C B 3 NC/144M A CE BW BW CLK A NC/512M B GW OE ADSP 2 D A C DQP NC V V V V V V V NC/1G DQP C DDQ SS SS SS SS SS DDQ B DQ DQ V V V V V V V DQ DQ D C C DDQ DD SS SS SS DD DDQ B B DQ DQ V V V V V V V DQ DQ E C C DDQ DD SS SS SS DD DDQ B B F DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B G DQ
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Pin Definitions Name IO Description A , A , A Input- Address inputs used to select one of the address locations. Sampled at the 0 1 [2] Synchronous rising edge of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE 1 2 3 are sampled active. A1: A0 are fed to the two-bit counter. BW , BW Input- Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes A B BW , BW Synchronous to the SRAM. Sampled on the rising edge of CLK. C
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Pin Definitions (continued) Name IO Description V Ground Ground for the core of the device. SS V IO Ground Ground for the IO circuitry. SSQ V IO Power Supply Power supply for the IO circuitry. DDQ MODE Input- Selects burst order. When tied to GND selects linear burst sequence. When tied Static to V or left floating selects interleaved burst sequence. This is a strap pin and DD must remain static during device operation. Mode pin has an internal pull u
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F The write signals (GW, BWE, and ) and ADV inputs are Burst Sequences BW X ignored during this first cycle. The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F ADSP triggered write accesses require two clock cycles to provides a two-bit wraparound counter, fed by A , that [1:0] complete. If GW is asserted LOW on the second clock rise, the implements either an interleaved or linear burst sequence. The data presented to the DQ inputs is written into the interleave
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F [4, 5, 6, 7, 8] Truth Table Operation Add. Used CE CE CE ZZ ADSP ADSC ADV WRITE OE CLK DQ 1 2 3 Deselect Cycle, Power Down None H X X L X L X X X L-H Tri-State Deselect Cycle, Power Down None L L X L L X X X X L-H Tri-State Deselect Cycle, Power Down None L X H L L X X X X L-H Tri-State Deselect Cycle, Power Down None L L X L H L X X X L-H Tri-State Deselect Cycle, Power Down None L X H L H L X X X L-H Tri-State Sleep Mode, Power Down None X X X H X X
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F [6, 9] Truth Table for Read/Write Function (CY7C1386D/CY7C1386F) GW BWE BW BW BW BW D C B A Read H H XXX X Read H L HHH H Write Byte A – (DQ and DQP) H L HHH L A A Write Byte B – (DQ and DQP)H L H H L H B B Write Bytes B, A H L H H L L Write Byte C – (DQ and DQP)H L H L H H C C Write Bytes C, A H L H L H L Write Bytes C, B H L H L L H Write Bytes C, B, A H L H L L L Write Byte D – (DQ and DQP)H L L H H H D D Write Bytes D, A H L L H H L Write Bytes D, B
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Test Data-In (TDI) IEEE 1149.1 Serial Boundary Scan (JTAG) The TDI ball is used to serially input information into the The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F registers and can be connected to the input of any of the incorporates a serial boundary scan test access port (TAP). registers. The register between TDI and TDO is chosen by the This part is fully compliant with 1149.1. The TAP operates instruction that is loaded into the TAP instruction regis
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F When the TAP controller is in the Capture-IR state, the two the IDCODE to be shifted out of the device when the TAP least significant bits are loaded with a binary ‘01’ pattern to controller enters the Shift-DR state. allow for fault isolation of the board-level serial test data path. The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test Bypass Register logic reset state. To save time
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F the TAP controller, it will directly control the state of the output register. When the EXTEST instruction is entered, this bit will (Q-bus) pins, when the EXTEST is entered as the current directly control the output Q-bus pins. Note that this bit is instruction. When HIGH, it will enable the output buffers to preset HIGH to enable the output when the device is powered drive the output bus. When LOW, this bit will place the output up, and also when the T
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels .................................................V to 3.3V Input pulse levels.................................................V to 2.5V SS SS Input rise and fall times .................................................. 1 ns Input rise and fall time .....................................................1 ns Input timing reference levels...........................................1.5
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Identification Register Definitions CY7C1386D/CY7C1386F CY7C1387D/CY7C1387F Instruction Field Description (512K × 36) (1M × 18) Revision Number (31:29) 000 000 Describes the version number [13] Device Depth (28:24) 01011 01011 Reserved for internal use. Device Width (23:18) 119-BGA 101110 101110 Defines the memory type and architecture. Device Width (23:18) 165-FBGA 000110 000110 Defines the memory type and architecture. Cypress Device ID (17:12) 10010
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F [14, 15] 119-Ball BGA Boundary Scan Order Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 23 F6 45 G4 67 L1 H4 2 T4 24E7 46A4 68 M2 3 T5 25D7 47 G3 69N1 4T6 26 H7 48 C3 70 P1 5 R5 27 G6 49B2 71K1 6 L5 28E6 50B3 72 L2 7R6 29 D6 51 A3 73 N2 8 U630 C7 52 C274 P2 9 R7 31B7 53A2 75 R3 10 T7 32 C6 54 B1 76 T1 11 P6 33 A6 55 C1 77 R1 12 N7 34 C5 56 D2 78 T2 13 M6 35 B5 57 E1 79 L3 14 L7 36 G5 58 F2 80 R2 15 K6 37 B6 59 G1 81 T3 16 P7 38 D4 60 H2 82 L
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F [14, 16] 165-Ball BGA Boundary Scan Order Bit # Ball ID Bit # Ball ID Bit # Ball ID 1N6 31 D10 61 G1 2N7 32 C11 62 D2 3N10 33 A11 63 E2 4P11 34 B11 64 F2 5P8 35 A10 65 G2 6R8 36 B10 66 H1 7R9 37 A9 67 H3 8P9 38 B9 68 J1 9 P10 39 C10 69 K1 10 R10 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 A7 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 A6 75 M2 16 K11 46 B5 76 N1 17 J11 47 A5 77 N2 18 M10 48 A4 78 P1 19 L10 49 B4 79 R1 20 K10 50 B3 80 R2 21 J10 51
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F DC Input Voltage ................................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW) ........................................ 20 mA Exceeding the maximum ratings may impair the useful life of Static Discharge Voltage.......................................... > 2001V the device. For user guidelines, not tested. (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Latch-up Curre
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F [19] Capacitance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Unit Max. Max Max C Input Capacitance T = 25°C, f = 1 MHz, 5 8 9 pF IN A V = 3.3V DD C Clock Input Capacitance 5 8 9 pF CLK V = 2.5V DDQ C Input/Output Capacitance 5 8 9 pF IO [19] Thermal Resistance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Unit Package Package Package Θ Thermal Resistance Test conditions follow standard 28.66 23.8 20.7 °C/W JA (Jun
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F [20, 21] Switching Characteristics Over the Operating Range –250 –200 –167 Description Unit Parameter Min Max Min Max Min Max [22] t V (Typical) to the First Access 11 1 ms POWER DD Clock t Clock Cycle Time 4.0 5.0 6.0 ns CYC t Clock HIGH 1.7 2.0 2.2 ns CH t Clock LOW 1.7 2.0 2.2 ns CL Output Times t Data Output Valid after CLK Rise 2.6 3.0 3.4 ns CO t Data Output Hold after CLK Rise 1.0 1.3 1.3 ns DOH [23, 24, 25] t Clock to Low-Z 1.0 1.3 1.3 ns CLZ [
