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CY7C1020BN
32K x 16 Static RAM
Features Functional Description
•High speed The CY7C1020BN is a high-performance CMOS static RAM
organized as 32,768 words by 16 bits. This device has an
—t = 12, 15 ns
AA
automatic power-down feature that significantly reduces
• CMOS for optimum speed/power
power consumption when deselected.
• Low active power
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
— 825 mW (max.)
(BLE) is LOW, then
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CY7C1020BN Selection Guide 7C1020BN-12 7C1020BN-15 Maximum Access Time (ns) 12 15 Maximum Operating Current (mA) 140 130 Maximum CMOS Standby Current (mA) 3 3 L 0.5 0.5 Current into Outputs (LOW)......................................... 20 mA Maximum Ratings Static Discharge Voltage............................................ >2001V (Above which the useful life may be impaired. For user guide- (per MIL-STD-883, Method 3015) lines, not tested.) Latch-Up Current..................................
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CY7C1020BN AC Test Loads and Waveforms R 481 Ω R 481 Ω ALL INPUT PULSES 5V 5V 3.0V 90% 90% OUTPUT OUTPUT 10% 10% R2 R2 GND 30 pF 5 pF 255 Ω 255 Ω INCLUDING INCLUDING JIG AND JIG AND Rise Time: 1 V/ns Fall Time: 1 V/ns SCOPE SCOPE (b) (a) 167 1.73V OUTPUT Equivalent to: THÉVENIN EQUIVALENT 30 pF [5] Switching Characteristics Over the Operating Range 7C1020BN-12 7C1020BN-15 Parameter Description Min. Max. Min. Max. Unit Read Cycle t Read Cycle Time 12 15 ns RC t Address to Data Valid 12 15 ns AA
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CY7C1020BN Switching Waveforms [9, 10] Read Cycle No. 1 t RC ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID DATA VALID [10, 11] Read Cycle No. 2 (OE Controlled) ADDRESS t RC CE t ACE OE t HZOE t DOE BHE, BLE t LZOE t HZCE t DBE t LZBE t HZBE HIGH IMPEDANCE HIGH IMPEDANCE DATA OUT DATA VALID t LZCE t PD t IICC PU CC V CC 50% 50% SUPPLY IISB CURRENT SB Notes: 9. Device is continuously selected. OE, CE, BHE and/or BHE = V . IL 10. WE is HIGH for read cycle. 11. Address valid prior to or coinc
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CY7C1020BN Switching Waveforms (continued) [12, 13] Write Cycle No. 1 (CE Controlled) t WC ADDRESS t t SA SCE CE t AW t HA t PWE WE t BW BHE,BLE t t SD HD DATA I/O Write Cycle No. 2 (BLE or BHE Controlled) t WC ADDRESS t t SA BW BHE,BLE t AW t HA t PWE WE t SCE CE t t SD HD DATA I/O Notes: 12. Data I/O is high impedance if OE or BHE and/or BLE= V . IH 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 001-06443 Rev. ** Page 5 of
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CY7C1020BN Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) t WC ADDRESS t SCE CE t AW t HA t SA t PWE WE t BW BHE, BLE t HZWE t t SD HD DATA I/O t LZWE Truth Table CE OE WE BLE BHE I/O –I/O I/O –I/O Mode Power 1 8 9 16 H X X X X High Z High Z Power-Down Standby (I ) SB L L H L L Data Out Data Out Read – All bits Active (I ) CC L H Data Out High Z Read – Lower bits only Active (I ) CC H L High Z Data Out Read – Upper bits only Active (I ) CC L X L L L Data In Data In
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CY7C1020BN Package Diagrams 44-Lead (400-Mil) Molded SOJ (51-85082) 51-85082-*B 44-Pin TSOP II (51-85087) 51-85087-*A All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-06443 Rev. ** Page 7 of 8 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embo
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CY7C1020BN Document History Page Document Title: CY7C1020BN 32K x 16 Static RAM Document #: 001-06443 Issue Orig. of REV. ECN NO. Date Change Description of Change ** 426812 See ECN NXR New Data Sheet Document #: 001-06443 Rev. ** Page 8 of 8 [+] Feedback
