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CY7C1019BN
128K x 8 Static RAM
Features Functional Description
•High speed The CY7C1019BN is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory
—t = 12, 15 ns
AA
expansion is provided by an active LOW Chip Enable (CE), an
• CMOS for optimum speed/power
active LOW Output Enable (OE), and three-state drivers. This
device has an automatic power-down feature that significantly
• Center power/ground pinout
reduces power consumption when deselected.
• Automatic po
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CY7C1019BN Selection Guide 7C1019BN-12 7C1019BN-15 Unit Maximum Access Time 12 15 ns Maximum Operating Current 140 130 mA Maximum Standby Current 10 10 mA L 1 1 mA Current into Outputs (LOW)......................................... 20 mA Maximum Ratings Static Discharge Voltage............................................ >2001V (Above which the useful life may be impaired. For user guide- (per MIL-STD-883, Method 3015) lines, not tested.) Latch-Up Current.......................................
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CY7C1019BN AC Test Loads and Waveforms R1 480Ω ALL INPUT PULSES R1 480Ω 5V 5V 3.0V 90% 90% OUTPUT OUTPUT 10% 10% R2 R2 GND 30 pF 5 pF 255Ω 255Ω ≤ 3 ns ≤ 3 ns INCLUDING INCLUDING JIG AND JIG AND SCOPE SCOPE (b) (a) Equivalent to: THÉVENIN EQUIVALENT 167Ω 1.73V OUTPUT [4] Switching Characteristics Over the Operating Range -12 -15 Parameter Description Min. Max. Min. Max. Unit Read Cycle t Read Cycle Time 12 15 ns RC t Address to Data Valid 12 15 ns AA t Data Hold from Address Change 3 3 ns OHA t
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CY7C1019BN Data Retention Characteristics Over the Operating Range (L Version Only) Parameter Description Conditions Min. Max. Unit V V for Data Retention No input may exceed V + 0.5V 2.0 V DR CC CC V = V = 2.0V, CC DR I Data Retention Current 300 µA CCDR > V – 0.3V, CE CC [3] t Chip Deselect to Data Retention Time V > V – 0.3V or V < 0.3V 0 ns CDR IN CC IN t Operation Recovery Time 200 µs R Data Retention Waveform DATA RETENTION MODE 3.0V 3.0V V V > 2V CC DR t t CDR R CE Switching Waveform
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CY7C1019BN Switching Waveforms (continued) [12, 13] Write Cycle No. 1 (CE Controlled) t WC ADDRESS t SCE CE t SA t SCE t t AW HA t PWE WE t t SD HD DATA I/O DATA VALID [12, 13] Write Cycle No. 2 (WE Controlled, OE HIGH During Write) t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE OE t SD t HD DATA I/O DATA VALID IN NOTE 14 t HZOE Notes: 12. Data I/O is high impedance if OE = V . IH 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 14. During th
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CY7C1019BN Switching Waveforms (continued) [13] Write Cycle No. 3 (WE Controlled, OE LOW) t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE t t SD HD NOTE 14 DATA I/O DATA VALID t t LZWE HZWE Truth Table CE OE WE I/O –I/O Mode Power 0 7 H X X High Z Power-Down Standby (I ) SB L L H Data Out Read Active (I ) CC L X L Data In Write Active (I ) CC L H H High Z Selected, Outputs Disabled Active (I ) CC Ordering Information Speed Package Operating (ns) Ordering Code Diagram Package Type Range 12 CY7C10
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CY7C1019BN Package Diagrams 32-pin (400-mil) Molded SOJ (51-85033) 51-85033-A 51-85033-*B 32-pin TSOP II (51-85095) 51-85095-** All product or company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-06425 Rev. ** Page 7 of 8 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuit
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CY7C1019BN Document History Page Document Title: CY7C1019BN 128K x 8 Static RAM Document Number: 001-06425 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 423847 See ECN NXR New Data Sheet Document #: 001-06425 Rev. ** Page 8 of 8 [+] Feedback
