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®
CY62158EV30 MoBL
8-Mbit (1024K x 8) Static RAM
[2]
Features Functional Description
• Very high speed: 45 ns The CY62158EV30 is a high performance CMOS static RAM
organized as 1024K words by 8 bits. This device features
— Wide voltage range: 2.20V–3.60V
advanced circuit design to provide ultra low active current.
®
• Pin compatible with CY62158DV30
This is ideal for providing More Battery Life™ (MoBL ) in
• Ultra low standby power portable applications such as cellular telephones. The device
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® CY62158EV30 MoBL [3] Pin Configurations 48-Ball VFBGA 44-Pin TSOPII Top View Top View 1 4 2 3 5 6 44 A 1 A 4 5 43 A 2 A 3 6 A A A NC OE CE 2 0 1 2 A 42 3 A A 2 7 41 4 OE A 1 40 NC 5 A A A CE NC NC CE B 3 4 0 2 1 39 6 A8 CE 1 38 NC NC 7 C IO NC A A NC IO 5 6 37 0 4 NC 8 NC 36 IO 9 IO 0 7 35 10 A V IO V IO CC IO SS A D 1 6 IO 7 17 5 1 34 11 V V CC SS 33 V 12 V SS CC V V IO NC A E IO SS 32 CC 16 IO 13 IO 2 6 2 5 IO 31 IO 14 3 4 NC 30 15 NC F A A IO NC NC IO 14 15 3 7 29 NC NC 16 28 A WE 17 9 1
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® CY62158EV30 MoBL Output Current into Outputs (LOW)............................. 20 mA Maximum Ratings Static Discharge Voltage............................................ >2001V Exceeding the maximum ratings may impair the useful life of (MIL-STD-883, Method 3015) the device. These user guidelines are not tested. Latch up Current...................................................... >200 mA Storage Temperature ..................................–65°C to +150°C Operating Range Ambient Temperat
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® CY62158EV30 MoBL [9] Thermal Resistance Parameter Description Test Conditions BGA TSOP II Unit Θ Thermal Resistance Still Air, soldered on a 3 x 4.5 inch, 72 76.88 °C/W JA (Junction to Ambient) two-layer printed circuit board Θ Thermal Resistance 8.86 13.52 °C/W JC (Junction to Case) AC Test Loads and Waveforms R1 ALL INPUT PULSES V CC V CC 90% 90% OUTPUT 10% 10% GND R2 Fall time: 1 V/ns 30 pF Rise Time: 1 V/ns INCLUDING JIG AND Equivalent to: THÉVENIN EQUIVALENT SCOPE R TH V OUTPUT TH
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® CY62158EV30 MoBL [11] Switching Characteristics (Over the Operating Range) 45 ns Parameter Description Unit Min Max Read Cycle t Read Cycle Time 45 ns RC t Address to Data Valid 45 ns AA t Data Hold from Address Change 10 ns OHA t CE LOW and CE HIGH to Data Valid 45 ns ACE 1 2 t OE LOW to Data Valid 22 ns DOE [12] t OE LOW to Low Z 5ns LZOE [12, 13] t OE HIGH to High Z 18 ns HZOE [12] t CE LOW and CE HIGH to Low Z 10 ns LZCE 1 2 [12, 13] t CE HIGH or CE LOW to High Z 18 ns HZCE 1 2 t CE L
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® CY62158EV30 MoBL Switching Waveforms [15, 16] Read Cycle No. 1 (Address Transition Controlled) t RC ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID DATA VALID [16, 17] Read Cycle No. 2 (OE Controlled) ADDRESS t RC CE 1 CE 2 t ACE OE t HZOE t DOE t HZCE t LZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA OUT DATA VALID t LZCE t PD V CC t I PU CC SUPPLY 50% 50% I CURRENT SB Notes 15. Device is continuously selected. OE, CE = V , CE = V . 1 IL 2 IH 16. WE is HIGH for read cycle. 17. Address valid before
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® CY62158EV30 MoBL Switching Waveforms (continued) [14, 18, 19] Write Cycle No. 1 (WE Controlled) t WC ADDRESS t SCE CE 1 CE 2 t t AW HA t t SA PWE WE OE t SD t HD VALID DATA DATA IO NOTE 20 t HZOE [14, 18, 19] Write Cycle No. 2 (CE or CE Controlled) 1 2 t WC ADDRESS t SCE CE 1 t SA CE 2 t t AW HA t PWE WE OE t t SD HD DATA IO VALID DATA Notes 18. Data IO is high impedance if OE = V . IH 19. If CE goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in high impedance state
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® CY62158EV30 MoBL Switching Waveforms (continued) [19] Write Cycle No. 3 (WE Controlled, OE LOW) t WC ADDRESS t SCE CE 1 CE 2 t t AW HA t t SA PWE WE t t SD HD DATA IO NOTE 20 VALID DATA t t HZWE LZWE Truth Table CE CE WE OE Inputs/Outputs Mode Power 1 2 H X X X High Z Deselect/Power Down Standby (I ) SB X L X X High Z Deselect/Power Down Standby (I ) SB L H H L Data Out Read Active (I ) CC L H H H High Z Output Disabled Active (I ) CC L H L X Data in Write Active (I ) CC Ordering Information
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® CY62158EV30 MoBL Package Diagrams Figure 1. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150 BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 1 2346 5 65 4 3 2 1 A A B B C C D D E E F F G G H H 1.875 A A B 0.75 6.00±0.10 3.75 B 6.00±0.10 0.15(4X) SEATING PLANE C 51-85150-*D Document #: 38-05578 Rev. *D Page 9 of 11 [+] Feedback 0.25 C 8.00±0.10 0.26 MAX. 0.55 MAX. 0.21±0.05 1.00 MAX 0.10 C 8.00±0.10 5.25 0.75 2.625
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® CY62158EV30 MoBL Package Diagrams (continued) Figure 2. 44-Pin TSOP II, 51-85087 51-85087-*A MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05578 Rev. *D Page 10 of 11 © Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes
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® CY62158EV30 MoBL Document History Page ® Document Title: CY62158EV30 MoBL , 8-Mbit (1024K x 8) Static RAM Document Number: 38-05578 Orig. of REV. ECN NO. Issue Date Description of Change Change ** 270329 See ECN PCI New Data Sheet *A 291271 See ECN SYT Converted from Advance Information to Preliminary Changed I from 4 to 4.5 µA CCDR *B 444306 See ECN NXR Converted from Preliminary to Final. Removed 35 ns speed bin Removed “L” bin. Removed 44 pin TSOP II package Included 48 pin TSOP I packa
