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TMS320C6201
Digital Signal Processor
Silicon Errata
SPRZ153
November 2000
Copyright 2000, Texas Instruments Incorporated
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TMS320C6201 Silicon Errata SPRZ153 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 Quality and Reliability Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 TMX Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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TMS320C6201 Silicon Errata SPRZ153 Advisory 2.1.19 PMEMC: Branch from External to Internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Advisory 2.1.21 DMA: DMA Data Block Corrupted After Start Zero Transfer Count . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 Silicon Revision 2.0 Known Design Exceptions to Functional Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Advisory 2.0.1 Program Fetch: Cache Modes Not
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TMS320C6201 Silicon Errata SPRZ153 1 Introduction This document describes the silicon updates to the functional specifications for the TMS320C6201 silicon releases 3.1, 3.0, 2.1, and 2.0. 1.1 Quality and Reliability Conditions TMX Definition Texas Instruments (TI) does not warranty either (1) electrical performance to specification, or (2) product reliability for products classified as “TMX.” By definition, the product has not completed data sheet verification or reliability performance qualifi
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TMS320C6201 Silicon Errata SPRZ153 1.2 Revision Identification The device revision can be determined by the lot trace code marked on the top of the package. The location for the lot trace codes for the GJL package is shown in Figure 1 and the revision numbers are listed in Table 1. Figure 1. Example, Lot Trace Code for TMS320C6201 DSP DSP TMS320C6201GJL TMS320C6201GJL Cxx–YMLLLLS C31–YMLLLLS Lot trace code Lot trace code with revision 3.1 NOTE: Qualified devices are marked with the letters “TMS
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TMS320C6201 Silicon Errata SPRZ153 2 Changes to the TMS320C6201 Data Sheet (literature number SPRS051) Table 2. Timing Requirements for Interrupt Response Cycles C6201B NO NO. UNIT UNIT MIN MAX 4 t Delay time, CLKOUT2 low to IACK valid –4 6 ns d(CKO2L-IACKV) 5 t Delay time, CLKOUT2 low to INUMx valid 6 ns d(CKO2L-INUMV) 6 t Delay time, CLKOUT2 low to INUMx invalid –4 ns d(CKO2L-INUMIV) Table 3. JTAG Test-Port Timing C6201, C6201B NO. NO. UNIT UNIT MIN MAX 1 T Cycle time, TCK 50 ns c(TCK) 4 T Hol
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TMS320C6201 Silicon Errata SPRZ153 Figure 3. SBSRAM Write Timing (1/2 Rate SSCLK) (See Note) SSCLK 1 2 CE 3 4 BE_ [3:0] BE1 BE3 BE2 BE4 5 6 EA [21:2] A1 A2 A3 A4 13 14 ED [31:0] Q2 Q1 Q3 Q4 9 10 SSADS SSOE 15 16 SSWE NOTE: The CEx output setup and hold times are specified to be accurate relative to the clock cycle to which they are referenced, since these timings are specified as minimums. However, the CE output setup and hold time may be greater than that shown in the data sheet in multiples o
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TMS320C6201 Silicon Errata SPRZ153 3 Silicon Revision 3.1 Known Design Exceptions to Functional Specifications Advisory 3.1.1 Issues When Pausing at a Block Boundary Revision(s) Affected: 3.1, 3.0, 2.1, and 2.0 Details: The following problems exist when a DMA channel is paused at a block boundary: • DMA does not flush internal FIFO when a channel is paused across block boundary. As a result, data from old and new blocks of that channel are in FIFO simultaneously. This prevents other channels fro
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TMS320C6201 Silicon Errata SPRZ153 Advisory 3.1.3 DMA Multiframe Split-mode Transfers Source Address Indexing Not Functional Revision(s) Affected: 3.1, 3.0, 2.1, and 2.0 Details: If a DMA channel is configured to do a multiframe split-mode transfer with SRC_DIR = Index (11b), the source address is always modified using the Element Index, even during the last element transfer of a frame. The transfer of the last element in a frame should index the source address using the Frame Index instead of t
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TMS320C6201 Silicon Errata SPRZ153 Advisory 3.1.6 DMA Paused During Emulation Halt Revision(s) Affected: 3.1, 3.0, 2.1, and 2.0 Details: When running an autoinitialized transfer, the DMA write state machine is halted during an emulation halt regardless of the value of EMOD in the DMA Channel Primary Control Register. The read state machine functions properly in this case. The problem exists only at block boundaries. If EMOD = 1, this problem is irrelevant since the DMA channel is expected to pau
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TMS320C6201 Silicon Errata SPRZ153 Alternative: If a 64M-bit SDRAM is located in CE3, avoid using the last 1K byte in the CE3 memory map (0x03FFFC00). Advisory 3.1.9 Cache During Emulation With Extremely Slow External Memory Revision(s) Affected: 3.1, 3.0, 2.1, and 2.0 Details: If a program requests fetch packet “A” followed immediately by fetch packet “B”, and all of the following four conditions are true: 1. A and B are separated by a multiple of 64K in memory (i.e., they will occupy the same
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TMS320C6201 Silicon Errata SPRZ153 4 Silicon Revision 3.0 Known Design Exceptions to Functional Specifications Advisory 3.0.8 EMIF: Inverted SDCLK and SSCLK at Speeds Above 175 MHz Revision(s) Affected: 3.0, 2.1, and 2.0 Details: A speedpath in the device causes SDCLK and SSCLK to start up 180 degrees out-of-phase (effectively inverted) from the desired waveform. Normally, EMIF outputs are delayed 1/2 CPU clock from the rising edge of SDCLK/SSCLK to give it adequate hold time while maintaining m
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TMS320C6201 Silicon Errata SPRZ153 EMIF: Inverted SDCLK and SSCLK at Speeds Above 175 MHz (Continued) 2. On SBSRAM/SDRAM reads, data will be sampled on the falling edge before the rising edge that would be expected. In this case, the input setup time for data at the C62x is reduced by 1 CPU cycle. Note that this case can be compounded with Case 1. The control signals could be latched one SSCLK/SDCLK cycle (2 CPU cycles) late by the memories. Thus, the setup could be reduced by up to 3 CPU cycle
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TMS320C6201 Silicon Errata SPRZ153 EMIF: Inverted SDCLK and SSCLK at Speeds Above 175 MHz (Continued) Alternate Workaround: The following alternate workarounds can help for certain board and layout configurations. • Using faster (125 MHz or PC100) SDRAMs and/or SBSRAMs will reduce the chances of data corruption and/or increase the frequency at which reliable memory operation can be observed. Operation is not specified to be reliable across operating conditions and different samples of memory and
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TMS320C6201 Silicon Errata SPRZ153 5 Silicon Revision 2.1 Known Design Exceptions to Functional Specifications Advisory 2.1.1 EMIF: CE Space Crossing on Continuous Request Not Allowed Revision(s) Affected: 2.1 and 2.0 Details: Any continuous request of the EMIF cannot cross CE address space boundaries. This condition can result in bad data read, or writing to the wrong CE. (Internal Reference Numbers 2600 and 3421) Workaround: CPU Program Fetch: The simplest fix is for all external program to re
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TMS320C6201 Silicon Errata SPRZ153 EMIF: SDRAM Invalid Access (Continued) Workaround: Avoid use of multiple CE spaces of SDRAM within a single refresh period. Advisory 2.1.4 DMA: RSYNC Cleared Late for Frame-synchronized Transfer Revision(s) Affected: 2.1 and 2.0 In a frame-synchronized transfer, RSYNC is only cleared after the beginning of last write transfer. It should occur after the start of the first read transfer in the synchronized frame. (Internal reference number 0267) Workaround: Wait
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TMS320C6201 Silicon Errata SPRZ153 McBSP: DXR to XSR Copy Not Generated (Continued) Example: Configure the DMA as follows: (a) For half-word/byte-size accesses with right justification on receive data: – ch_A: /* for transmit */ src_address = mem_out; dst_address = DXR; Element_size = WORDAddress_inc_mode = indexIndex_reg_value = 2 /* change this to 1 for byte writes */ – ch_B : /* for receive */ src_address = DRR; dst_address = mem_in; Element_size = HALF /* change this to BYTE for 8-b element
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TMS320C6201 Silicon Errata SPRZ153 McBSP: DXR to XSR Copy Not Generated (Continued) (c) For byte-size writes with right justification on receive data: – ch_A: /* for transmit */ dst_address = DXR+3; /* 0x018C0007 for McBSP0 or 0x01900007 for McBSP1 */ Element_size = WORDAddress_inc_mode = indexIndex_reg_value = 1 – ch_B : /* for receive */ src_address = DRR+3 /* 0x018C0003 for McBSP0 or 0x01900003 for McBSP1 */ dst_address = mem_in; Element_size = BYTE; Address_inc_mode = = inc_by_ element_size
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TMS320C6201 Silicon Errata SPRZ153 Advisory 2.1.7 DMA Channel 0 Multiframe Split-Mode Incompletion Revision(s) Affected: 2.1 and 2.0 Details: If DMA Channel 0 is configured to perform a multiframe split-mode transfer, it is possible for the last element of the last frame of the Receive Read to not be transferred. After the last element of the last frame of the Transmit Write Transfer, the element count is reloaded into the Channel 0 Transfer Counter Register, which may allow for the Transmit Rea
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TMS320C6201 Silicon Errata SPRZ153 Advisory 2.1.11 McBSP: Incorrect Law Companding Value Revision(s) Affected: 2.1 and 2.0 Details: The C6201 McBSP -Law/A-Law companding hardware produces an incorrectly expanded -Law value. McBSP receives -Law value 0111 1111, representing a mid-scale analog value. Expanded 16-bit data is 1000 0000 0000 0000, representing a most negative value. Expected value is 0000 0000 0000 0000. McBSP expands µ -Law 1111 1111 (also mid-scale value) correctly. -Law works
