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®
Intel IXP2800 Network
Processor
Hardware Reference Manual
August 2004
Order Number: 278882-010
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Revision History Date Revision Description March 2002 001 First release for IXP2800 Customer Information Book V 0.4 May 2002 002 Update for the IXA SDK 3.0 release. August 2002 003 Update for the IXA SDK 3.0 Pre-Release 4. November 2002 004 Update for the IXA SDK 3.0 Pre-Release 5. May 2003 005 Update for the IXA SDK 3.1 Alpha Release September 2003 006 Update for the IXA SDK 3.5 Pre-Release 1 Added information about Receiver and Transmitter October 2003 007 Interoperation with Framers and Swit
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Contents Contents 1 Introduction..................................................................................................................................25 1.1 About This Document .........................................................................................................25 1.2 Related Documentation ......................................................................................................25 1.3 Terminology ........................................................
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Contents 2.6 Scratchpad Memory............................................................................................................56 2.6.1 Scratchpad Atomic Operations..............................................................................57 2.6.2 Ring Commands....................................................................................................57 2.7 Media and Switch Fabric Interface ....................................................................................
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Contents 3.2.7 Power Management...............................................................................................81 3.2.8 Debugging .............................................................................................................81 3.2.9 JTAG......................................................................................................................81 3.3 Memory Management...........................................................................................
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Contents 3.6.2.3.4 Write-Back versus Write-Through........................................101 3.6.2.4 Round-Robin Replacement Algorithm .................................................102 3.6.2.5 Parity Protection...................................................................................102 3.6.2.6 Atomic Accesses..................................................................................102 3.6.3 Data Cache and Mini-Data Cache Control .............................................
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Contents 3.11.5 I/O Transaction ....................................................................................................130 3.11.6 Hash Access........................................................................................................130 3.11.7 Gasket Local CSR ...............................................................................................131 3.11.8 Interrupt ..................................................................................................
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Contents 4.3.1 Byte Align.............................................................................................................174 4.3.2 CAM.....................................................................................................................176 4.4 CRC Unit...........................................................................................................................179 4.5 Event Signals............................................................................
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Contents 6.2.1 Internal Interface..................................................................................................209 6.2.2 Number of Channels............................................................................................209 6.2.3 Coprocessor and/or SRAMs Attached to a Channel............................................209 6.3 SRAM Controller Configurations.......................................................................................209 6.4 Command Overview
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Contents 8.2.5 Rx_Thread_Freelist_Timeout_# ..........................................................................256 8.2.6 Receive Operation Summary...............................................................................256 8.2.7 Receive Flow Control Status ...............................................................................258 8.2.7.1 SPI-4....................................................................................................258 8.2.7.2 CSIX..................
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Contents 8.7.2.3 Single IXP2800 Network Processor.....................................................289 8.8 Interface to Command and Push and Pull Buses .............................................................290 8.8.1 RBUF or MSF CSR to Microengine S_TRANSFER_IN Register for Instruction:.291 8.8.2 Microengine S_TRANSFER_OUT Register to TBUF or MSF CSR for Instruction:.....................................................................................291 8.8.3 Microengine to MSF CSR for
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Contents 9 PCI Unit.......................................................................................................................................319 9.1 Overview...........................................................................................................................319 9.2 PCI Pin Protocol Interface Block.......................................................................................321 9.2.1 PCI Commands .........................................................
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Contents 9.4.2 Push/Pull Command Bus Target Interface...........................................................345 9.4.2.1 Command Bus Master Access to Local Configuration Registers ........345 9.4.2.2 Command Bus Master Access to Local Control and Status Registers...................................................................................346 9.4.2.3 Command Bus Master Direct Access to PCI Bus ................................346 9.4.2.3.1 PCI Address Generation for IO and MEM Cycles....
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Contents 10.3.2 PCI-Initiated Reset...............................................................................................366 10.3.3 Watchdog Timer-Initiated Reset ..........................................................................366 10.3.3.1 Slave Network Processor (Non-Central Function)...............................367 10.3.3.2 Master Network Processor (PCI Host, Central Function) ....................367 10.3.3.3 Master Network Processor (Central Function).....................
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Contents 11.4.6.7 ME01 Events Target ID(100001) / Design Block #(1001)....................410 11.4.6.8 ME02 Events Target ID(100010) / Design Block #(1001)....................411 11.4.6.9 ME03 Events Target ID(100011) / Design Block #(1001)....................411 11.4.6.10 ME04 Events Target ID(100100) / Design Block #(1001)....................412 11.4.6.11 ME05 Events Target ID(100101) / Design Block #(1001)....................412 11.4.6.12 ME06 Events Target ID(100110) / Design Block #(1001)..
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Contents Figures 1 IXP2800 Network Processor Functional Block Diagram ............................................................28 2 IXP2800 Network Processor Detailed Diagram..........................................................................29 3 Intel XScale® Core 4-GB (32-Bit) Address Space .....................................................................32 4 Microengine Block Diagram..................................................................................................
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Contents 48 An Interface Topology with Intel / AMCC* SONET/SDH Device ..............................................158 49 Mode 3 Second Interface Topology with Intel / AMCC* SONET/SDH Device..........................159 50 Mode 3 Single Write Transfer Followed by Read (B0) .............................................................160 51 Mode 3 Single Read Transfer Followed by Write (B0) .............................................................161 52 An Interface Topology with Intel / AMC
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Contents 98 CSIX Flow Control Interface — FCIFIFO and FCEFIFO in Full Duplex Mode .........................277 99 CSIX Flow Control Interface — FCIFIFO and FCEFIFO in Simplex Mode ..............................278 100 MSF to Command and Push and Pull Buses Interface Block Diagram....................................290 101 Basic I/O Capability of the Intel® IXP2800 Network Processor................................................292 102 Simplex Configuration ......................................
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Contents Tables 1 Data Terminology .......................................................................................................................26 2 Longword Formats......................................................................................................................26 3 IXP2800 Network Processor Microengine Bus Arrangement.....................................................35 4 Next Neighbor Write as a Function of CTX_ENABLE[NN_MODE] ..................................
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Contents ® 47 Byte-Enable Generation by the Intel XScale Core for Byte Writes in Little- and Big-Endian Systems .................................................................................................................123 ® 48 Byte-Enable Generation by the Intel XScale Core for Word Writes in Little- and Big-Endian Systems .................................................................................................................124 49 CMB Write Command to CPP Command Conversion .
