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TMS320TCI648x Serial RapidIO (SRIO)
User's Guide
Literature Number: SPRUE13A
September 2006
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2 SPRUE13A–September 2006 Submit Documentation Feedback
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Contents Preface.............................................................................................................................. 14 1 Overview .................................................................................................................. 16 1.1 General RapidIO System...................................................................................... 16 1.2 RapidIO Feature Support in SRIO..........................................................................
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5.23 LSU Interrupt Condition Clear Register (LSU_ICCR) .................................................... 141 5.24 Error, Reset, and Special Event Interrupt Condition Status Register (ERR_RST_EVNT_ICSR).................................................................................... 142 5.25 Error, Reset, and Special Event Interrupt Condition Clear Register (ERR_RST_EVNT_ICCR) ................................................................................... 143 5.26 DOORBELLn Interrupt Co
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5.69 Port Link Maintenance Request CSR n (SPn_LM_REQ)................................................ 200 5.70 Port Link Maintenance Response CSR n (SPn_LM_RESP) ............................................ 201 5.71 Port Local AckID Status CSR n (SPn_ACKID_STAT) ................................................... 202 5.72 Port Error and Status CSR n (SPn_ERR_STAT)......................................................... 203 5.73 Port Control CSR n (SPn_CTL).......................................
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List of Figures 1 RapidIO Architectural Hierarchy.......................................................................................... 17 2 RapidIO Interconnect Architecture ....................................................................................... 18 3 Serial RapidIO Device to Device Interface Diagrams ................................................................. 19 4 SRIO Peripheral Block Diagram.............................................................................
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50 RX CPPI Interrupt Condition Status and Clear Registers............................................................. 89 51 TX CPPI Interrupt Condition Status and Clear Registers............................................................. 89 52 LSU Interrupt Condition Status and Clear Registers .................................................................. 90 53 Error, Reset, and Special Event Interrupt Condition Status and Clear Registers ................................. 91 54 Doorbell 0
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102 LSUn FLOW_MASK Fields.............................................................................................. 162 103 Queue n Transmit DMA Head Descriptor Pointer Register (QUEUEn_TXDMA_HDP) ......................... 164 104 Queue n Transmit DMA Completion Pointer Register (QUEUEn_TXDMA_CP) ................................. 165 105 Queue n Receive DMA Head Descriptor Pointer Register (QUEUEn_RXDMA_HDP).......................... 166 106 Queue n Receive DMA Completion Pointer Register (Q
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155 Port IP Mode CSR (SP_IP_MODE) - Address Offset 12004h...................................................... 231 156 Port IP Prescaler Register (IP_PRESCAL) - Address Offset 12008h ............................................. 233 157 Port-Write-In Capture CSRs............................................................................................. 234 158 Port Reset Option CSR n (SPn_RST_OPT) .......................................................................... 235 159 Port Control
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List of Tables 1 TI Devices Supported By This Document............................................................................... 20 2 Registers Checked for Multicast DeviceID.............................................................................. 21 3 Packet Types ............................................................................................................... 25 4 Pin Description............................................................................................
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50 RapidIO DEVICEID1 Register (DEVICEID_REG1) Field Descriptions............................................ 121 51 RapidIO DEVICEID2 Register (DEVICEID_REG2) Field Descriptions............................................ 122 52 PF_16B_CNTL Registers................................................................................................ 123 53 Packet Forwarding Register n for 16-Bit DeviceIDs (PF_16B_CNTLn) Field Descriptions..................... 123 54 PF_8B_CNTL Registers .............
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99 LSUn_REG6 Registers and the Associated LSUs ................................................................... 161 100 LSUn Control Register 6 (LSUn_REG6) Field Descriptions ........................................................ 161 101 LSUn_FLOW_MASKS Registers and the Associated LSUs........................................................ 162 102 LSUn Congestion Control Flow Mask Register (LSUn_FLOW_MASKS) Field Descriptions ................... 162 103 LSUn FLOW_MASK Fields..............
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150 Error Reporting Block Header Register (ERR_RPT_BH) Field Descriptions ..................................... 209 151 Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions ...................................... 210 152 Logical/Transport Layer Error Enable CSR (ERR_EN) Field Descriptions ....................................... 212 153 Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) Field Descriptions ................... 214 154 Logical/Transport Layer Address Capt
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Preface SPRUE13A–September 2006 Read This First About This Manual ® This document describes the Serial RapidIO (SRIO) peripheral on the TMS320TCI648x™ devices. Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number represents 40 hexadecimal (decimal 64): 40h. • Registers in this document are shown in figures and described in tables. – Each register figure shows a rectangle divided into fields that
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www.ti.com Related Documentation From Texas Instruments Trademarks TMS320TCI648x, C6000, TMS320C62x, TMS320C67x, TMS320C6000, Code Composer Studio are trademarks of Texas Instruments. RapidIO is a registered trademark of RapidIO Trade Association. InfiniBand is a trademark of the InfiniBand Trade Association. SPRUE13A–September 2006 Read This First 15 Submit Documentation Feedback
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User's Guide SPRUE13A–September 2006 Serial RapidIO (SRIO) 1 Overview The RapidIO peripheral used in the TMS320TCI648x is called a serial RapidIO (SRIO). This chapter describes the general operation of a RapidIO system, how this module is connected to the outside world, the definitions of terms used within this document, and the features supported and not supported for SRIO. 1.1 General RapidIO System ® RapidIO is a non-proprietary high-bandwidth system level interconnect. It is a packet-switche
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www.ti.com Overview Figure 1. RapidIO Architectural Hierarchy Logical specification Globally Future I/O Message Information necessary for the end point shared logical to process the transaction (i.e., transaction system passing memory spec type, size, physical address) Transport specification Common Information to transport packet from end transport to end in the system (i.e., routing address) spec Physical specification Future 8/16 1x/4x Information necessary to move packet physical between two
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www.ti.com Overview 1.1.2 RapidIO Interconnect Architecture The interconnect architecture is defined as a packet switched protocol independent of a physical layer implementation. Figure 2 illustrates the interconnection system. Figure 2. RapidIO Interconnect Architecture Host Subsystem I/O Control Subsystem InfiniBand™ HCA Memory Memory IO Control ASIC/FPGA Memory Processor Processor Host Host Processor Processor To System Area Network RapidIO RapidIO to Memory Switch InfiniBand RapidIO RapidIO
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www.ti.com Overview Figure 3. Serial RapidIO Device to Device Interface Diagrams 1x Device 1x Device TD[0] RD[0] TD[0] RD[0] RD[0] TD[0] RD[0] TD[0] Serial RapidIO 1x Device to 1x Device Interface Diagram 4x Device 4x Device TD[0-3] RD[0-3] TD[0-3] RD[0-3] RD[0-3] TD[0-3] RD[0-3] TD[0-3] Serial RapidIO 4x Device to 4x Device Interface Diagram 1.2 RapidIO Feature Support in SRIO Features Supported in SRIO Peripheral: • RapidIO Interconnect Specification V1.2 compliance, Errata 1.2 • Physical Laye
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www.ti.com Overview Features Not Supported: • Compliance with the Global Shared Memory specification (GSM) • 8/16 LP-LVDS compatible • Destination support of RapidIO Atomic Operations • Simultaneous mixing of frequencies between 1x ports (all ports must be the same frequency) • Target atomic operations (including increment, decrement, test-and-swap, set, and clear) for internal L2 memory and registers 1.3 Standards The SRIO peripheral is compliant to V1.2 of the RapidIO Interconnect Specificatio
