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PRELIMINARY draft 2
Sundance Technology
ST201
Fast Ethernet MAC
FEATURES GENERAL DESCRIPTION
The ST201 is a single-chip, full duplex, 10/
• Single chip 10/100BASE, half or full duplex
100Mbps Ethernet MAC incorporating a 32-bit PCI
Ethernet Media Access Controller
including bus master support. The ST201 is
• IEEE 802.3u compliant MII
designed for use in a variety of applications rang-
ing from workstation NICs, networking equipment
• IEEE 802.3x full duplex flow control
such as switches or rout
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Sundance Technology ST201 PRELIMINARY draft 2 BLOCK DIAGRAM PCI MII Status/Control Registers RSTN TXD[3..0] PCICLK TXEN GNTN TXCLK Tx Tx Tx IDSEL RXD[3..0] DMA FIFO MAC INTAN RXCLK WAKE RXER REQN RXDV AD[31..0] CRS Rx Rx Rx PCI CBEN[3:0] COL DMA FIFO MAC Bus PAR MDC I/F FRAMEN MDIO IRDYN Statistic Registers TRDYN EEPROM DEVSELN EEDO STOPN EEDI PERRN EESK SERRN EECS VDET MISCELLANEOUS EXPANSION ROM GPIO0 ED[7..0] GPIO1 EA[15..0] EWEN RSTOUT EOEN X25I X25O PHY CLK25 PHYLNKN POWER PHYDPLXN PHYSPDN
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Sundance Technology ST201 PRELIMINARY draft 2 ORDERING INFORMATION Sundance products are available in several combinations of packages and operating temperature ranges. The order number is formed by a combination of the elements below ST201 K C TEMPERATURE RANGE C=Commercial (0 to +70C) PACKAGE TYPE K=Plastic Quad Flat Pack DEVICE NUMBER/DESCRIPTION ST201 Fast Ethernet MAC 3
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Sundance Technology ST201 PRELIMINARY draft 2 PIN DIAGRAM 4
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Sundance Technology ST201 PRELIMINARY draft 2 PIN DESIGNATIONS PIN PIN PIN PIN PIN NAME PIN NAME PIN NAME PIN NAME NO. NO. NO. NO. 1 VCC (5V) 33 AD9 65 EA2 97 RXCLK 2 CBEN3 34 GND (5V) 66 EA3 98 RXDV 3 IDSEL 35 AD8 67 EA4 99 RXD0 4 AD23 36 CBEN0 68 EA5 100 RXD1 5 AD22 37 AD7 69 EA6 101 RXD2 6 AD21 38 AD6 70 EA7 102 RXD3 7 AD20 39 AD5 71 EA8 103 GND (5V) 8 GND (5V) 40 GND (3.3V) 72 EA9/ 104 MDC LEDPWRN 9 AD19 41 VDET 73 EA10/ 105 GND (3.3V) LEDLNKN 10 AD18 42 AD4 74 EA
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Sundance Technology ST201 PRELIMINARY draft 2 PIN DESCRIPTIONS PIN NAME PIN TYPE PIN DESCRIPTION PCI INTERFACE RSTN INPUT Reset, asserted LOW. RSTN will cause the ST201 to reset all of its functional blocks. RSTN must be asserted for a minimum duration of 10 PCICLK cycles. PCICLK INPUT PCI Bus Clock. This clock is used to drive the PCI bus interfaces and the internal DMA logic. All bus signals are sampled on the rising edges of PCICLK. PCICLK can operate from 0MHz to 33MHz. GNTN INPUT PCI Bu
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Sundance Technology ST201 PRELIMINARY draft 2 PIN NAME PIN TYPE PIN DESCRIPTION TRDYN IN/OUT Target Ready, asserted LOW. A bus target asserts TRDYN to indicate valid read data phases, and to indicate it is ready to accept data during write data phases. A bus master will monitor TRDYN. DEVSELN IN/OUT Device Select, asserted LOW. The ST201 asserts DEVSELN when it is selected as a target during a bus transaction. It monitors DEVSELN for any target to acknowledge a bus transaction initiated by
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Sundance Technology ST201 PRELIMINARY draft 2 PIN NAME PIN TYPE PIN DESCRIPTION COL INPUT Collision. COL is asserted by the PHY to a signal collision condition is detected on the physical medium. COL is asynchronous to RXCLK and TXCLK. MDC OUTPUT Management Data Clock. MDC is used to synchronize the read and write operations of MDIO. MDIO IN/OUT Management Data Input/Output. MDIO carries management data for the management port read and write operations. PHY INTERFACE PHYLNKN INPUT PHY Link S
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Sundance Technology ST201 PRELIMINARY draft 2 PIN NAME PIN TYPE PIN DESCRIPTION LEDPWRN OUTPUT Power Status LED. (This pin is shared with EA9). The operation of this pin varies based on the setting in the I/O Registers, AsicCtrl bit 14 (the LEDMode bit). In Mode 0, LOW when power is applied, and toggling when frame transmission is in progress. In Mode 1, this pin is always LOW when power is applied. LEDLNKN OUTPUT Link Status LED. (This pin is shared with EA10). The operation of this pin va
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Sundance Technology ST201 PRELIMINARY draft 2 CSMA/CD, allowing data to be transmitted on ACRONYMS AND GLOSSARY demand. An optional flow control mechanism in full LAN Local Area Network duplex mode is provided via the 802.3x MAC Con- MAC Media Access Control Layer, or a trol PAUSE function. Additionally, the MAC also device implementing the functions performs the following functions in either half or full of this layer (a Media Access Con- duplex mode: troller) • Optional transmit FCS generatio
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Sundance Technology ST201 PRELIMINARY draft 2 PCI BUS INTERFACE complete frame must be transferred from the host system memory to the TxFIFO again by TxDMA The PCI Bus Interface (PBI) implements the proce- Logic. dures and algorithms needed to link the ST201 to a PCI bus. The ST201 can be either a PCI bus mas- RXDMA LOGIC ter or slave. The PBI is also responsible for manag- The ST201 supports a multi-frame, multi-fragment ing the DMA interfaces and the host processors DMA scatter process. Descr
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Sundance Technology ST201 PRELIMINARY draft 2 EXPANSION ROM INTERFACE • loBaseAddress sets the I/O base address for the ST201 registers. The ST201 provides support for an optional Expan- • MemBaseAddress sets the memory base address sion ROM. The ST201 supports the Atmel for the ST201 registers. AT29C512 (64K x 8) Flash EPROM device. • ExpRomBaseAddress sets the base address and The Expansion ROM is configured through the PCI size for an installed expansion ROM, if any. configuration register
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Sundance Technology ST201 PRELIMINARY draft 2 dress register. Setting the ReceiveBroadcast and ity to inhibit transmission of MAC data frames for a ReceiveMulticast bits in the ReceiveMode register specified period of time. The PAUSE frame format will allow the ST201 to receive all broadcast and is defined as shown in Figure 1. multicast frames, respectively. The ReceiveMultic- LENGTH astHash bit in ReceiveMode enables a filtering FIELD (BYTES) mechanism for Ethernet multicast frames. This fil-
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Sundance Technology ST201 PRELIMINARY draft 2 TXDMA AND FRAME TRANSMISSION The resulting linked list of TFDs is referred to as the TxDMAList, as shown in Figure 3. The TxDMA block transfers frame data from a host system to the ST201 based on a linked list of frame HOST SYSTEM MEMORY descriptors called TFDs. The frame to be transmit- ted is divided into data fragments (or buffers) within TFD 1 the host system’s memory. The host system cre- ates a list of TFDs, also in system memory, where each TF
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Sundance Technology ST201 PRELIMINARY draft 2 The TxDMAListPtr I/O register within the ST201 probably set TxDMAIndicate to generate an inter- contains the physical address that points to the rupt. However, if during the TxDMA process of this head of the TxDMAList. TxDMAListPtr must point frame, the host system added a new TFD to the to addresses which are on 8-byte boundaries. A end of the list, it might clear TxDMAIndicate in the value of zero in the TxDMAListPtr register implies currently acti
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Sundance Technology ST201 PRELIMINARY draft 2 are independent of each other in general. A special contain pointers to the fragment buffers into which case is when a transmit under run occurs. In this the ST201 is to place receive data, as shown in case the current frame being transmitted is the only Figure 4. frame in the TxFIFO. When a transmit under run HOST SYSTEM MEMORY occurs, the ST201 stops TxDMA operation and generates an interrupt with a TxUnderrun error flagged in TxStatus. The host sy
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Sundance Technology ST201 PRELIMINARY draft 2 received and transferred by RxDMA, a RxDMA- tions. Similar to TxDMA, the RxDMA Logic can be Complete interrupt will be generated for each controlled by the RxDMAHalt and RxDMAResume frame. bits. The host system should set the RxDMAHalt bit before modifying the list pointers in the RxD- HOST SYSTEM MEMORY MAList. The RxDMA Logic will return to the idle state when the RxDMAListPtr register is zero. RFD 1 For RxDMA lists configured as a ring, the host s
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Sundance Technology ST201 PRELIMINARY draft 2 Systems using the ST201 can be programmed to The host system can then perform memory copies generate an interrupt based upon the number of out of the RFD buffer in parallel with the RxDMA bytes that have been received in a frame. The operation. RxEarlyThresh register sets the value for early INTERRUPTS receive threshold. As soon as the number of bytes that have been received is greater than the value in The term “interrupt” is used loosely to refer t
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Sundance Technology ST201 PRELIMINARY draft 2 this statistic. STATISTICS • CarrierSenseErrors: Frames that were transmit- The ST201 implements 16 statistics counters of ted without error but experienced a loss of car- various widths. Each statistic implemented com- rier are counted by this statistic. plies to the corresponding definition given in the IEEE 802.3 standard. Setting the StatisticsEnable RECEIVE STATISTICS bit in the MACCtrl register enables the gathering of • FramesReceivedOk: Frame
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Sundance Technology ST201 PRELIMINARY draft 2 disable the use of MWI and MRL. MWIDisable and ST201 optionally supports this state deter- MRLDisable are cleared by default, enabling MWI mined by the D1Support bit in the ConfigParm and MRL. word in EEPROM. The D1 state allows transi- tion back to D0 with no delay. In this state, the The ST201 provides a set of registers that control ST201 responds to PCI configuration the PCI burst behavior. These registers allow a accesses, to allow the system
