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®
Intel 440GX AGPset
Design Guide
March 1999
Order Number: 290651-001
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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, me
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Contents 1 Introduction ................................................................................................................1-1 1.1 About This Design Guide..............................................................................1-1 1.2 References....................................................................................................1-2 ® ® ® 1.3 Intel Pentium II Processor / Intel 440GX AGPset Overview ...................1-3 ® ® 1.3.1 Intel Pentium II Processor.......
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2.6 Validation ....................................................................................................2-15 2.6.1 Flight Time Measurement ..............................................................2-15 2.6.2 Signal Quality Measurement..........................................................2-16 2.7 Timing Analysis...........................................................................................2-17 2.8 AGP Layout and Routing Guidelines ...................................
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3.7 82371EB (PIIX4E).......................................................................................3-16 3.7.1 PIIX4E Connections.......................................................................3-16 3.7.2 IDE Routing Guidelines..................................................................3-20 3.7.2.1 Cabling..........................................................................3-20 3.7.2.2 Motherboard .................................................................3-20 3.7.3
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4.3 Debug Features ............................................................................................4-2 ® ® 4.3.1 Intel Pentium II Processor LAI Issue ...........................................4-2 4.3.2 Debug Logic Recommendations......................................................4-4 4.3.2.1 Debug Considerations ....................................................4-5 4.3.3 Debug Layout ..................................................................................4-5 4.3.3.1 De
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Figures ® ® ® 1-1 Intel Pentium II Processor / Intel 440GX AGPset System Block Diagram..................................................................................1-4 2-1 Major Signal Sections (82443GX Top View).................................................2-1 ® 2-2 Example ATX Placement for a UP Pentium II processor/ ® Intel 440GX AGPset Design .......................................................................2-2 ® ® 2-3 Example NLX Placement for a UP Intel Pentium II processor /
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Tables 2-1 Recommended Trace Lengths for Single Processor Design........................2-7 2-2 Recommended Trace Lengths for Dual Processor Designs2.......................2-8 2-3 SET Trace Length Requirements .................................................................2-9 2-4 Recommended 100 MHz System Flight Time Specs .................................2-13 2-5 System Timing Requirements for Validating Setup/Hold Windows ............2-16 ® ® 2-6 Ringback Guidelines at the Intel Pentium II
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Revision History Date Revision Description 3/99 -001 Initial Release. ® Intel 440GX AGPset Design Guide ix
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® x Intel 440GX AGPset Design Guide
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1 Introduction
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Introduction Introduction 1 ® ® ® This document provides design guidelines for developing Intel Pentium II processor / Intel 440GX AGPset based systems. Motherboard and memory subsystem design guidelines are covered. Special design recommendations and concerns are presented. Likely design issues have been identified and included here in a checklist format to alleviate problems during the debug phase. One reference board design is presented: • Dual Processor (DP), 4 DIMM design ® ® ® These de
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Introduction 1.2 References ® ® • Intel Pentium II Processor Datasheet ® • Intel 440GX AGPset Datasheet (WWW; order number 290638) • Intel 82371EB PCI-to-ISA/IDE Xcelerator (PIIX4) Datasheet (WWW; order number 290562) • Intel Architecture Software Developer’s Manual, Volume 1; Basic Architecture (order number 243190) • Intel Architecture Software Developer’s Manual, Volume 2; Instruction Set Reference (order number 243191) • Intel Architecture Software Developer’s Manual, Volume 3; System Prog
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Introduction ® ® ® 1.3 Intel Pentium II Processor / Intel 440GX AGPset Overview ® ® ® The following is a list of features that a Intel Pentium II processor / Intel 440GX System will provide: ® ® • Full Support for up to two Intel Pentium II processors, with system bus frequencies of 100 MHz ® • Intel 440GX AGPset — 82443GX Host Bridge Controller (GX) — 82371EB PCI ISA IDE Accelerator (PIIX4E) • 100 MHz Memory Interface: A wide range of DRAM support including — 64-bit memory data interface pl
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Introduction ® ® Intel introduced the Intel Pentium II processor as 350/100 and 400/100 speeds with 512 KB L2 cache versions. ® 1.3.2 Intel 440GX AGPset ® ® ® • The Intel 440GX AGPset is the fourth generation chipset based on the Intel Pentium Pro ® ® processor architecture. It has been designed to interface with the Intel Pentium II processor’s system bus at 100 MHz. Along with its Host-to-PCI bridge interface, the 82443GX host bridge controller has been optimized with a 100 MHz SDRAM memo
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Introduction ® Figure 1-1 shows a block diagram of a typical platform based on the Intel 440GX AGPset. The ® ® 82443GX system bus interface supports up to two Intel Pentium II processors at the maximum bus frequency of 100 MHz. The physical interface design is based on the GTL+ specification and is ® compatible with the Intel 440GX AGPset solution. The 82443GX provides an optimized 72-bit DRAM interface (64-bit Data plus ECC). This interface supports 3.3V DRAM technologies. The 82443GX is d
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Introduction 1.3.2.4 PCI Interface The 82443GX PCI interface is 33 MHz Revision 2.1 compliant and supports up to five external PCI bus masters in addition to the I/O bridge (PIIX4E). 1.3.2.5 System Clocking The 82443GX operates the system bus interface at 100 MHz, PCI at 33 MHz and AGP at 66/133 MHz. The 443GX clocking scheme uses an external clock synthesizer which produces reference clocks for the system bus and PCI interfaces. The 82443GX produces a single 100 MHz SDRAM clock output which
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Introduction Manageability features in each of these four technology areas combine to form the Wired for Management Baseline Specification. A copy of the Wired for Management Baseline Specification can be obtained from: ftp://download.intel.com/ial/wfm/baseline.pdf An on-line Design Guide is available at: http://developer.intel.com/ial/WfM/design/index.htm Future versions of the specification, which preserve today's investments, will be available at this site. 1.3.3.1 Instrumentation A compo
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Introduction 1.3.3.3 Remote Wake-Up If a PC supports a reduced power state, it must be possible to bring the system to a fully powered state in which all management interfaces are available. Typically, the LAN adapter recognizes a special packet as a signal to wake up the system. This reference design utilizes a Wake on LAN (WOL) Header to provide standby power to the NIC and the interface for the wake up signal. The physical connection to the NIC and motherboard is via a WOL Cable provided
