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S/G No. : CP005P-010G1
Service Guide
Colour Television
CHASSIS : CP-005
Model :
DTP-14V1/V2/V3/V5/C3/C4/C5TF
20V1/V3/C4/C5TF
21V1/V2/V4/V6/C6TF
21 V4
14/21 V2 14/20 V3
14/20/21 V1
14 V5
14 C3 14/20 C5
14/20 C4
21 C6
If you need further information ( IC, Circuit descriptions or troubleshooting . . .)
about this model, Please visit our web site.( http://svc.dwe.co.kr)
Specifications
DTP-14V1TF
ITEM
DTP-14V2TF
DTP-21V1TF
DTP-20V1TF
DTP-14V3TF
DTP-21V2TF
DTP-20V3TF
DTP-14V5TF
DTP-
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PRODUCT SAFETY SERVICING GUIDELINES FOR AUDIO - VIDEO PRODUCTS CAUTION : DO NOT ATTEMPT TO MODIFY THIS PRODUCT IN ANY WAY. SUBJECT : X-RADIATION NEVER PERFORM CUSTOMIZED INSTALLATIONS WITHOUT MANUFAC- TURER'S APPROVAL. UNAUTHORIZED MODIFICATIONS WILL NOT ONLY VOID 1. BE SURE PROCEDURES AND INSTRUCTIONS TO ALL SERVICE PERSON- THE WARRANTY, BUT MAY LEAD TO YOUR BEING LIABLE FOR ANT RESULT- NEL COVER THE SUBJECT OF X-RADIATION. THE ONLY POTENTIAL ING PROPERTY DAMAGE OR USER INJURY. SOURCE OF
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PRODUCT SAFETY SERVICING GUIDELINES FOR COLOR TELEVISION RECEIVERS CAUTION : Do not attempt to modify this product in any way. Unau- GRAPHIC SYMBOLS : thorized modifications will not only void the warranty, but may lead to your being liable for any resulting property damage or user injury. The lightning flash with arrowhead symbol, Service work should be performed only after you are thoroughly within an equilateral triangle, is intended to alert familiar with all of the following safety checks
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4. Wall and shelf mounted installations using a commercial mounting SUBJECT : IMPLOSION kit, must follow the factory approved mounting instructions. A 1. All direct viewed picture tubes are equipped with an integral implo- receiver mounted to a shelf or platform must retain its original sion protection system, but care should be taken to avoid damage feet(or the equivalent thickness in spacers) to provide adequate are flow across the bottom, bolts or screws used for fasteners during installation
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JS02 JS01 CP-005 CHASSIS ANTENNA AV JACK SCART JACK U101 SF101 IF SPEAKER TUNER PICTURE S/F RF INPUT 3W 8OHM SF102 5V 33V SOUND S/F I501 SPEAKER AGC STV2238 3W 8OHM I702 EEPROM DATA CLK 2 SPK OTION - BUS CONTROL AT24C16 - PIF SCL SDA CVBS - SIF ST-BY I701 OSD R - AUDIO/VIDEO SWICHES R OSD G R U-COM With TELETEXT - LUMINANCE PROCESSING I704 ST92195 OSD B REMOT I901 H.OUT - PAL/SECAM/NTSC CHROMA DECODER G G IR BL REMOCON E TDA6103Q CRT - DEFLECTION PROCESSOR PREAMP HALH TONE V.OUT B B SCREEN Vc
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ENTER SERVICE MODE ! 1. Select the Pr 91. "#
2. Adjust “Sparpness” to 0.
3. Enter the service mode using the following keys.
" R !! G !! MENU. !! !!
$
"
"% $# $# $ &&
$ ' 1. AFT 1) Set a Signal Generator with RF FREQUENCY = 38.9MHz, 34.2MHz (L’) RF OUTPUT LEVEL = 80 5 dBuV ± ± ± ± System = PAL f
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2. SCREEN 1) Receive the Retma pattern and heat run over 15 minutes. 2) Adjust the “R, G BIAS, R, G DRIVE” to 0, “B BIAS” to 127, “B DRIVE” to 32. Adjust the screen volume that the Retma pattern reach to the cut-off point. 3. WHITE BALANCE 1) Receive the Full white pattern and heat run over 15 minutes. 2) Adjust the picture control at the point “Y” value of white balance instrument in 20cd/. 3) Enter the service mode. 4) Adjust “R BIAS, G BIAS” to x=288, y=301. 5) In order to
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6. GEOMETRY 6.1 VERTICAL CENTER 1) Set the TV to “NORMAL I” mode. 2) Enter the service mode. 3) Locate the cursor at “V. CENTER” then press “VOL +” or “VOL – “ keys to adjust the center line with the mechanical center marks of the CRT. 6.2 VERTICAL SIZE ∗ ∗ ∗ ∗ The VERTICAL CENTER adjustment has to be done in advance. 1) Receive the Retma pattern. 2) Set the TV to “NORAML I” mode. 3) Enter the service mode. 4) Locate the cursor at “V. SIZE” then press “VOL +” or VOL –“ keys to adju
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If EEPROM(I702) has been changed ; - Option data has to be changed and - all alignment function has to be readjusted. * The initial state of adjustment are as follows ; - V-Center, V-Size, H-Center, R, G, B, AFT = Center ( ) - AGC = * Service Remocon
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ST92195B 32-64K ROM HCMOS MCU WITH ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER ■ Register File based 8/16 bit Core Architecture with RUN, WFI, SLOW and HALT modes ■ 0°C to +70°C operating temperature range ■ Up to 24 MHz. operation @ 5V±10% ■ Min. instruction cycle time: 165ns at 24 MHz. ■ 32, 48, 56 or 64 Kbytes ROM ■ 256 bytes RAM of Register file (accumulators or index registers) ■ 256 bytes of on-chip static RAM PSDIP56 ■ 2, 6 or 8 Kbytes of TDSRAM (Teletext and Display Storage RAM) ■ 28 ful
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ST92195B - GENERAL INFORMATION 1 GENERAL INFORMATION 1.1 INTRODUCTION cy programmable via the CCU. In this mode, the power consumption of the device can be reduced The ST92195 microcontroller is developed and by more than 95% (Low power WFI). manufactured by STMicroelectronics using a pro- Halt Mode. When executing the HALT instruction, prietary n-well HCMOS process. Its performance and if the Watchdog is not enabled, the CPU and derives from the use of a flexible 256-register pro- its periphera
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ST92195B - GENERAL INFORMATION GENERAL DESCRIPTION (Cont’d) 1.1.7 Teletext, VPS and WSS Data Slicers 1.1.10 Serial Peripheral Interface (SPI) The three on-board data slicers using a single ex- The SPI bus is used to communicate with external ternal crystal are used to extract the Teletext, VPS devices via the SPI, or IC ² bus communication and WSS information from the video signal. Hard- standards. The SPI uses a single data line for data ware Hamming decoding is provided. input and output. A se
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ST92195B - GENERAL INFORMATION Figure 1. ST92195 Block Diagram Up to 64 I/O 8 P0[7:0] Kbytes ROM PORT 0 256 bytes I/O RAM P2[5:0] 6 PORT 2 Up to 8 I/O Kbytes P3[7:4] 4 TRI PORT 3 TDSRAM I/O P4[7:0] 8 256 bytes PORT 4 Register File 8/16-bit I/O 2 P5[1:0] CPU PORT 5 MMU NMI DATA INT[7:4] TXCF Interrupt SLICER INT2 Management INT0 & ACQUI- CVBS1 SITION ST9+ CORE UNIT OSCIN SYNC. OSCOUT RCCU EXTRAC- RESET TION RESETO 16-BIT VPS/WSS 1 WSCR TIMER/ DATA 1 WSCF WATCHDOG SLICER CVBS2 AIN[4:1] SD
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ST92195B - GENERAL INFORMATION 1.2 PIN DESCRIPTION Figure 2. 64-Pin Package Pin-Out 64 48 V GND 1 SS P4.7/PWM7/EXTRG/STOUT AIN4/P0.2 P4.6/PWM6 P0.1 P4.5/PWM5 P0.0 P4.4/PWM4 CSO/RESET0/P3.7 P4.3/PWM3/TSLU/HT P3.6 P4.2/PWM2 P3.5 P4.1/PWM1 P3.4 P4.0/PWM0 B VSYNC G HSYNC/CSYNC R AVDD1 FB PXFM SDO/SDI/P5.1 JTRST0 INT2/SCK/P5.0 GND V DD N.C. JTDO 16 16 32 *See Note 1 of pin description. N.C. = Not connected 10/202 V N.C. DD P0.3 N.C. P0.4 *WSCF P0.5 *VPP/WSCR P0.6 AVDD3 P0.7 TEST0 RESET MCFM P2.0/IN
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ST92195B - GENERAL INFORMATION PIN DESCRIPTION (Cont’d) RESET Reset (input, active low). The ST9+ is ini- PXFM Analog pin for the Display Pixel Frequency tialised by the Reset signal. With the deactivation Multiplier of RESET, program execution begins from the AVDD3 Analog VDD of PLL. This pin must be tied Program memory location pointed to by the vector to VDD externally to the ST92195. contained in program memory locations 00h and GND Digital circuit ground. 01h. AGND Analog circuit ground (mu
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ST92195B - GENERAL INFORMATION Figure 4. ST92195 Required External components VCC U1 82pF C1 1 56 P20 P21 P2.0/INT7 P2.1/INT5/AIN1 2 55 P22 1μF RESETN P2.2/INT0/AIN2 3 54 Y1 P07 P23 10k C2 R1 P0.7 P2.3/INT6/VS01 4 53 P06 P24 4Mhz P0.6 P2.4/NMI P05 5 52 P25 P0.5 P2.5/AIN3/INT4/VS02 6 51 P04 P0.4 OSCIN 82pF S1 C3 D1 P03 7 50 P0.3 OSCOUT 8 49 P02 P47 P0.2/AIN4 P4.7/PWM7/EXTRG/STOUT 1N4148 P01 9 48 P46 RST P0.1 P4.6/PWM6 10 47 P00 P45 P0.0 P4.5/PWM5 P37 11 46 P44 P3.7/RESETO/CSO P4.4/PWM4 12 45 P36
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ST92195B - GENERAL INFORMATION PIN DESCRIPTION (Cont’d) P0[7:0], P2[5:0], P3[7:4], P4[7:0], P5[1:0] Important: Note that open-drain outputs are for I/O Port Lines (Input/Output, TTL or CMOS com- logic levels only and are not true open drain. patible). 1.2.1 I/O Port Alternate Functions. 28 lines grouped into I/O ports, bit programmable Each pin of the I/O ports of the ST92195 may as- as general purpose I/O or as Alternate functions sume software programmable Alternate Functions (see I/O secti
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ST92195B - GENERAL INFORMATION 1.2.2 I/O Port Styles Pins Weak Pull-Up Port Style Reset Values P0[7:0] no Standard I/O BID / OD / TTL P2[5,4,3,2] no Standard I/O BID / OD / TTL P2[1,0] no Schmitt trigger BID / OD / TTL P3.7 yes Standard I/O AF / PP / TTL P3[6,5,4] no Standard I/O BID / OD / TTL P4[7:0] no Standard I/O BID / OD / TTL P5[1:0] no Standard I/O BID / OD / TTL Legend: AF= Alternate Function, BID = Bidirectional, OD = Open Drain PP = Push-Pull, TTL = TTL Standard Input Levels How to Re
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IC DESCRIPTION I801 POWER CONTROL MODULE DPM 001 TI KSE 14 13 12 11 10 6 5 4 3 2 1 PIN NO DESCRIPTION PIN NO DESCRIPTION 1 GATE DRIVE1 10 +12V INPUT 2 OCP 11 POWER CONTROL 3 SOURCE 12 NC 4 GND1 13 GND2 5 GATE 14 +133V INPUT 6 GATE DRIVE2
